{"title":"缺陷条件下辐射免疫CMOS逻辑族的灵敏度分析","authors":"Erik H. Ingermann, J. Frenzel","doi":"10.1109/VTEST.1993.313378","DOIUrl":null,"url":null,"abstract":"Simulation of resistive shorts is performed on a recently developed single event upset immune logic family. Critical resistances and resultant transition delay times are compared with those of traditional CMOS logic. Behavior of the logic under these simulated defects is discussed.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Sensitivity analysis of a radiation immune CMOS logic family under defect conditions\",\"authors\":\"Erik H. Ingermann, J. Frenzel\",\"doi\":\"10.1109/VTEST.1993.313378\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Simulation of resistive shorts is performed on a recently developed single event upset immune logic family. Critical resistances and resultant transition delay times are compared with those of traditional CMOS logic. Behavior of the logic under these simulated defects is discussed.<<ETX>>\",\"PeriodicalId\":283218,\"journal\":{\"name\":\"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium\",\"volume\":\"8 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-04-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VTEST.1993.313378\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTEST.1993.313378","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Sensitivity analysis of a radiation immune CMOS logic family under defect conditions
Simulation of resistive shorts is performed on a recently developed single event upset immune logic family. Critical resistances and resultant transition delay times are compared with those of traditional CMOS logic. Behavior of the logic under these simulated defects is discussed.<>
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