{"title":"基于反向传播的记忆空间池学习","authors":"O. Krestinskaya, A. P. James","doi":"10.1109/AICAS.2019.8771628","DOIUrl":null,"url":null,"abstract":"Spatial pooler is responsible for feature extraction in Hierarchical Temporal Memory (HTM). In this paper, we present analog backpropagation learning circuits integrated to the memristive circuit design of spatial pooler. Using 0.18μm CMOS technology and TiOx memristor models, the maximum on-chip area and power consumption of the proposed design are 8335.074μm2 and 51.55mW, respectively. The system is tested for a face recognition problem AR face database achieving a recognition accuracy of 90%.","PeriodicalId":273095,"journal":{"name":"2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"AnalogHTM: Memristive Spatial Pooler Learning with Backpropagation\",\"authors\":\"O. Krestinskaya, A. P. James\",\"doi\":\"10.1109/AICAS.2019.8771628\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Spatial pooler is responsible for feature extraction in Hierarchical Temporal Memory (HTM). In this paper, we present analog backpropagation learning circuits integrated to the memristive circuit design of spatial pooler. Using 0.18μm CMOS technology and TiOx memristor models, the maximum on-chip area and power consumption of the proposed design are 8335.074μm2 and 51.55mW, respectively. The system is tested for a face recognition problem AR face database achieving a recognition accuracy of 90%.\",\"PeriodicalId\":273095,\"journal\":{\"name\":\"2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)\",\"volume\":\"111 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/AICAS.2019.8771628\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/AICAS.2019.8771628","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
AnalogHTM: Memristive Spatial Pooler Learning with Backpropagation
Spatial pooler is responsible for feature extraction in Hierarchical Temporal Memory (HTM). In this paper, we present analog backpropagation learning circuits integrated to the memristive circuit design of spatial pooler. Using 0.18μm CMOS technology and TiOx memristor models, the maximum on-chip area and power consumption of the proposed design are 8335.074μm2 and 51.55mW, respectively. The system is tested for a face recognition problem AR face database achieving a recognition accuracy of 90%.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
