Pub Date : 2019-03-18DOI: 10.1109/AICAS.2019.8771512
G. Haessig, F. Galluppi, Xavier Lagorce, R. Benosman
This paper describes spike-based neural networks for optical flow and stereo estimation from Dynamic Vision Sensors data. These methods combine the Asynchronous Time-based Image Sensor with the SpiNNaker platform. The sensor generates spikes with sub-millisecond resolution in response to scene illumination changes. These spike are processed by a spiking neural network running on SpiNNaker with a 1 millisecond resolution to accurately determine the order and time difference of spikes from neighboring pixels, and therefore infer the velocity, direction or depth. The spiking neural networks are a variant of the Barlow-Levick method for optical flow estimation, and Marr& Poggio for the stereo matching.
{"title":"Neuromorphic networks on the SpiNNaker platform","authors":"G. Haessig, F. Galluppi, Xavier Lagorce, R. Benosman","doi":"10.1109/AICAS.2019.8771512","DOIUrl":"https://doi.org/10.1109/AICAS.2019.8771512","url":null,"abstract":"This paper describes spike-based neural networks for optical flow and stereo estimation from Dynamic Vision Sensors data. These methods combine the Asynchronous Time-based Image Sensor with the SpiNNaker platform. The sensor generates spikes with sub-millisecond resolution in response to scene illumination changes. These spike are processed by a spiking neural network running on SpiNNaker with a 1 millisecond resolution to accurately determine the order and time difference of spikes from neighboring pixels, and therefore infer the velocity, direction or depth. The spiking neural networks are a variant of the Barlow-Levick method for optical flow estimation, and Marr& Poggio for the stereo matching.","PeriodicalId":273095,"journal":{"name":"2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"511 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120932914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-18DOI: 10.1109/AICAS.2019.8771580
Dongchen Liang, Raphaela Kreiser, Carsten Nielsen, Ning Qiao, Yulia Sandamirskaya, G. Indiveri
Mixed-signal analog/digital neuromorphic circuits are characterized by ultra-low power consumption, real-time processing abilities, and low-latency response times. These features make them promising for robotic applications that require fast and power-efficient computing. However, the unavoidable variance inherently existing in the analog circuits makes it challenging to develop neural processing architectures able to perform complex computations robustly. In this paper, we present a spiking neural network architecture with spike-based learning that enables robust learning and recognition of visual patterns in noisy silicon neural substrate and noisy environments. The architecture is used to perform pattern recognition and inference after a training phase with computers and neuromorphic hardware in the loop. We validate the proposed system in a closed-loop hardware setup composed of neuromorphic vision sensors and processors, and we present experimental results that quantify its real-time and robust perception and action behavior.
{"title":"Robust Learning and Recognition of Visual Patterns in Neuromorphic Electronic Agents","authors":"Dongchen Liang, Raphaela Kreiser, Carsten Nielsen, Ning Qiao, Yulia Sandamirskaya, G. Indiveri","doi":"10.1109/AICAS.2019.8771580","DOIUrl":"https://doi.org/10.1109/AICAS.2019.8771580","url":null,"abstract":"Mixed-signal analog/digital neuromorphic circuits are characterized by ultra-low power consumption, real-time processing abilities, and low-latency response times. These features make them promising for robotic applications that require fast and power-efficient computing. However, the unavoidable variance inherently existing in the analog circuits makes it challenging to develop neural processing architectures able to perform complex computations robustly. In this paper, we present a spiking neural network architecture with spike-based learning that enables robust learning and recognition of visual patterns in noisy silicon neural substrate and noisy environments. The architecture is used to perform pattern recognition and inference after a training phase with computers and neuromorphic hardware in the loop. We validate the proposed system in a closed-loop hardware setup composed of neuromorphic vision sensors and processors, and we present experimental results that quantify its real-time and robust perception and action behavior.","PeriodicalId":273095,"journal":{"name":"2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127961045","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-18DOI: 10.1109/AICAS.2019.8771569
N. D. Truong, O. Kavehei
Electroencephalogram (EEG) neural activity recording has been widely used for diagnosing and monitoring epileptic patients. Ambulatory epileptic monitoring devices that can detect or even predict seizures play an important role for patients with intractable epilepsy. Though many EEG-based seizure detection algorithms have been proposed in the literature with high accuracy, their hardware implementations are constrained because of power consumption. Many commercial non-research EEG monitoring systems samples multiple electrodes at a relatively high rate and transmit the data either via a wire or wirelessly to an external signal processing unit. In this work, we studied how a reduced sampling precision affects the performance of our machine learning signal processing in seizure detection. To answer this question, we reduce the number of bits (precision) in an analog-to-digital converter (ADC) used in an EEG recorder. The outcome shows that the reduction of ADC precision down to 6-bit does not significantly reduce our convolutional neural network performance in detecting seizure onsets. As an indication of the performance, we achieved an area under the curve (AUC) more than 92% and above 96% on Freiburg Hospital and the Boston Children’s Hospital-MIT seizure datasets, respectively. A possible reduction in ADC precision not only contribute to energy consumption reduction, particularly if the data has to be transmitted, but also offers an improved computational efficacy regarding memory requirement and circuit area.
脑电图(EEG)神经活动记录已广泛应用于癫痫患者的诊断和监测。可以检测甚至预测癫痫发作的动态癫痫监测装置对难治性癫痫患者起着重要的作用。虽然文献中提出了许多基于脑电图的癫痫发作检测算法，但由于功耗的限制，它们的硬件实现受到限制。许多商用的非研究性脑电图监测系统以相对较高的速率对多个电极进行采样，并通过有线或无线方式将数据传输到外部信号处理单元。在这项工作中，我们研究了降低采样精度如何影响癫痫检测中机器学习信号处理的性能。为了回答这个问题，我们减少了脑电图记录仪中使用的模数转换器(ADC)的位数(精度)。结果表明，将ADC精度降低到6位并不会显著降低卷积神经网络检测癫痫发作的性能。作为性能指标，我们分别在Freiburg医院和Boston Children 's Hospital- mit癫痫发作数据集上实现了超过92%和96%的曲线下面积(AUC)。ADC精度的可能降低不仅有助于降低能耗，特别是在必须传输数据的情况下，而且还提供了关于内存要求和电路面积的改进的计算效率。
{"title":"Low Precision Electroencephalogram for Seizure Detection with Convolutional Neural Network","authors":"N. D. Truong, O. Kavehei","doi":"10.1109/AICAS.2019.8771569","DOIUrl":"https://doi.org/10.1109/AICAS.2019.8771569","url":null,"abstract":"Electroencephalogram (EEG) neural activity recording has been widely used for diagnosing and monitoring epileptic patients. Ambulatory epileptic monitoring devices that can detect or even predict seizures play an important role for patients with intractable epilepsy. Though many EEG-based seizure detection algorithms have been proposed in the literature with high accuracy, their hardware implementations are constrained because of power consumption. Many commercial non-research EEG monitoring systems samples multiple electrodes at a relatively high rate and transmit the data either via a wire or wirelessly to an external signal processing unit. In this work, we studied how a reduced sampling precision affects the performance of our machine learning signal processing in seizure detection. To answer this question, we reduce the number of bits (precision) in an analog-to-digital converter (ADC) used in an EEG recorder. The outcome shows that the reduction of ADC precision down to 6-bit does not significantly reduce our convolutional neural network performance in detecting seizure onsets. As an indication of the performance, we achieved an area under the curve (AUC) more than 92% and above 96% on Freiburg Hospital and the Boston Children’s Hospital-MIT seizure datasets, respectively. A possible reduction in ADC precision not only contribute to energy consumption reduction, particularly if the data has to be transmitted, but also offers an improved computational efficacy regarding memory requirement and circuit area.","PeriodicalId":273095,"journal":{"name":"2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130997786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-18DOI: 10.1109/AICAS.2019.8771613
Min-Hui Lin, C. Yeh, Chu-Han Lin, Chih-Hsiang Huang, Li-Wei Kang
Blocking artifact, characterized by visually noticeable changes in pixel values along block boundaries, is a general problem in block-based image/video compression systems. Various post-processing techniques have been proposed to reduce blocking artifacts, but most of them usually introduce excessive blurring or ringing effects. This paper presents a deep learning-based compression artifacts reduction (or deblocking) framework relying on multi-scale residual learning. Recent popular approaches usually train deep models using a per-pixel loss function with explicit image priors for directly producing deblocked images. Instead, we formulate the problem as learning the residuals (or the artifacts) between original and the corresponding compressed images. In our deep model, each input image is down-scaled first with blocking artifacts naturally reduced. Then, the learned SR (super-resolution) convolutional neural network (CNN) will be used to up-sample the down-scaled version. Finally, the up-scaled version (with less artifacts) and the original input are fed into the learned artifact prediction CNN to obtain the estimated blocking artifacts. As a result, the blocking artifacts can be successfully removed by subtracting the predicted artifacts from the input image while preserving most original visual details.
{"title":"Deep Multi-Scale Residual Learning-based Blocking Artifacts Reduction for Compressed Images","authors":"Min-Hui Lin, C. Yeh, Chu-Han Lin, Chih-Hsiang Huang, Li-Wei Kang","doi":"10.1109/AICAS.2019.8771613","DOIUrl":"https://doi.org/10.1109/AICAS.2019.8771613","url":null,"abstract":"Blocking artifact, characterized by visually noticeable changes in pixel values along block boundaries, is a general problem in block-based image/video compression systems. Various post-processing techniques have been proposed to reduce blocking artifacts, but most of them usually introduce excessive blurring or ringing effects. This paper presents a deep learning-based compression artifacts reduction (or deblocking) framework relying on multi-scale residual learning. Recent popular approaches usually train deep models using a per-pixel loss function with explicit image priors for directly producing deblocked images. Instead, we formulate the problem as learning the residuals (or the artifacts) between original and the corresponding compressed images. In our deep model, each input image is down-scaled first with blocking artifacts naturally reduced. Then, the learned SR (super-resolution) convolutional neural network (CNN) will be used to up-sample the down-scaled version. Finally, the up-scaled version (with less artifacts) and the original input are fed into the learned artifact prediction CNN to obtain the estimated blocking artifacts. As a result, the blocking artifacts can be successfully removed by subtracting the predicted artifacts from the input image while preserving most original visual details.","PeriodicalId":273095,"journal":{"name":"2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133689851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-18DOI: 10.1109/AICAS.2019.8771556
Yuheng Sun, T. Chiueh
Self-organizing feature map (SOFM) is a type of artificial neural network based on an unsupervised learning algorithm. In this work, we present a circuit for accelerating SOFM training, which forms the foundation for an effective, efficient, and flexible SOFM training platform for different network geometries, including array, rectangular, and binary tree. FPGA validation was also conducted to examine the speedup ratio of this circuit when compared with training using software. In addition, we applied our design to three applications: chromaticity diagram learning, MNIST handwritten numeral auto-labeling, and image vector quantization. All three experiments show that the proposed circuit architecture indeed provides a high-performance and cost-effective solution to SOFM training.
{"title":"A Flexible and High-Performance Self-Organizing Feature Map Training Acceleration Circuit and Its Applications","authors":"Yuheng Sun, T. Chiueh","doi":"10.1109/AICAS.2019.8771556","DOIUrl":"https://doi.org/10.1109/AICAS.2019.8771556","url":null,"abstract":"Self-organizing feature map (SOFM) is a type of artificial neural network based on an unsupervised learning algorithm. In this work, we present a circuit for accelerating SOFM training, which forms the foundation for an effective, efficient, and flexible SOFM training platform for different network geometries, including array, rectangular, and binary tree. FPGA validation was also conducted to examine the speedup ratio of this circuit when compared with training using software. In addition, we applied our design to three applications: chromaticity diagram learning, MNIST handwritten numeral auto-labeling, and image vector quantization. All three experiments show that the proposed circuit architecture indeed provides a high-performance and cost-effective solution to SOFM training.","PeriodicalId":273095,"journal":{"name":"2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133985426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-18DOI: 10.1109/AICAS.2019.8771586
Hai-Che Ting, H. Fang, Jia-Shung Wang
The HEVC (H.265) standard was finalized in April 2013, currently being as the prevalent video coding standard. One key contributor to the performance gain over H.264 is the intra prediction that extended a large number of prediction directions on various sizes of prediction units (PUs), thus at a cost of very high computational complexity. When HEVC has been emerged, several fast Intra prediction and Coding Unit (CU) size decision algorithms are being developed for practical applications. Actually, these two components would cost around 60% to 70% encoding time in the all-intra HEVC encoding. In this paper, a novel CNN-based solution is proposed and evaluated. The main idea is to elect a smallest set of adequate intra directions using our modified LeNet-5 CNN model, thus reduce the computational complexity of (further) rate distortion optimization to a tolerable limit. Besides, two filters are employed: the edge strength extractor in [4] and the early terminated CU partition in [7] to skip most of the unlikely directions and to decrease the number of CUs, respectively. The experimental results demonstrate that the proposed method provides a decrease of up to 66.59% computation with a slightly increase in the bit-rate (1.1% on average) and a little reduction of picture quality (0.109% on average in PSNR) at most.
{"title":"Complexity Reduction on HEVC Intra Mode Decision with modified LeNet-5","authors":"Hai-Che Ting, H. Fang, Jia-Shung Wang","doi":"10.1109/AICAS.2019.8771586","DOIUrl":"https://doi.org/10.1109/AICAS.2019.8771586","url":null,"abstract":"The HEVC (H.265) standard was finalized in April 2013, currently being as the prevalent video coding standard. One key contributor to the performance gain over H.264 is the intra prediction that extended a large number of prediction directions on various sizes of prediction units (PUs), thus at a cost of very high computational complexity. When HEVC has been emerged, several fast Intra prediction and Coding Unit (CU) size decision algorithms are being developed for practical applications. Actually, these two components would cost around 60% to 70% encoding time in the all-intra HEVC encoding. In this paper, a novel CNN-based solution is proposed and evaluated. The main idea is to elect a smallest set of adequate intra directions using our modified LeNet-5 CNN model, thus reduce the computational complexity of (further) rate distortion optimization to a tolerable limit. Besides, two filters are employed: the edge strength extractor in [4] and the early terminated CU partition in [7] to skip most of the unlikely directions and to decrease the number of CUs, respectively. The experimental results demonstrate that the proposed method provides a decrease of up to 66.59% computation with a slightly increase in the bit-rate (1.1% on average) and a little reduction of picture quality (0.109% on average in PSNR) at most.","PeriodicalId":273095,"journal":{"name":"2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121089562","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-18DOI: 10.1109/AICAS.2019.8771531
Tae-Sun Kim, Ji-Hoon Bae, M. Sunwoo
Recent advances in computing power made possible by developments of faster general-purpose graphics processing units (GPGPUs) have increased the complexity of convolutional neural network (CNN) models. However, because of the limited applications of the existing GPGPUs, CNN accelerators are becoming more important. The current accelerators focus on improvement in memory scheduling and architectures. Thus, the number of multiplier-accumulator (MAC) operations is not reduced. In this study, a new convolution layer operation algorithm is proposed using the coarse-to-fine method instead of hardware or architecture approaches. This algorithm is shown to reduce the MAC operations by 33%. However, the accuracy of the Top 1 is decreased only by 3% and the Top 5 only by 1%.
{"title":"Fast Convolution Algorithm for Convolutional Neural Networks","authors":"Tae-Sun Kim, Ji-Hoon Bae, M. Sunwoo","doi":"10.1109/AICAS.2019.8771531","DOIUrl":"https://doi.org/10.1109/AICAS.2019.8771531","url":null,"abstract":"Recent advances in computing power made possible by developments of faster general-purpose graphics processing units (GPGPUs) have increased the complexity of convolutional neural network (CNN) models. However, because of the limited applications of the existing GPGPUs, CNN accelerators are becoming more important. The current accelerators focus on improvement in memory scheduling and architectures. Thus, the number of multiplier-accumulator (MAC) operations is not reduced. In this study, a new convolution layer operation algorithm is proposed using the coarse-to-fine method instead of hardware or architecture approaches. This algorithm is shown to reduce the MAC operations by 33%. However, the accuracy of the Top 1 is decreased only by 3% and the Top 5 only by 1%.","PeriodicalId":273095,"journal":{"name":"2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126534479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-18DOI: 10.1109/AICAS.2019.8771594
Hussein Assaf, Y. Savaria, M. Sawan
Vector Matrix Multiplication (VMM) is a complex operation requiring large computational power to fulfill one iteration. Resistive computing; including memristors, is one solution to speed up VMM by optimizing the multiplication process into few steps despite the matrices’ sizes. In this paper, we propose an Adaptive Dot Product Engine (ADPE) algorithm based on memristors for enhancing the process of resistive computing in VMM. The algorithm showed 5% error on preliminary results with one on-line training step for one layered crossbar array circuit of memristors. However memristors require new fabrication technologies where the design and validation processes of systems using these devices remains challenging. A comparison of various available circuits emulating a memristor suitable for ADPE is presented and models were compared based on chip size, circuit elements used and operating frequency.
{"title":"Memristor Emulators for an Adaptive DPE Algorithm: Comparative Study","authors":"Hussein Assaf, Y. Savaria, M. Sawan","doi":"10.1109/AICAS.2019.8771594","DOIUrl":"https://doi.org/10.1109/AICAS.2019.8771594","url":null,"abstract":"Vector Matrix Multiplication (VMM) is a complex operation requiring large computational power to fulfill one iteration. Resistive computing; including memristors, is one solution to speed up VMM by optimizing the multiplication process into few steps despite the matrices’ sizes. In this paper, we propose an Adaptive Dot Product Engine (ADPE) algorithm based on memristors for enhancing the process of resistive computing in VMM. The algorithm showed 5% error on preliminary results with one on-line training step for one layered crossbar array circuit of memristors. However memristors require new fabrication technologies where the design and validation processes of systems using these devices remains challenging. A comparison of various available circuits emulating a memristor suitable for ADPE is presented and models were compared based on chip size, circuit elements used and operating frequency.","PeriodicalId":273095,"journal":{"name":"2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127832781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-03-18DOI: 10.1109/AICAS.2019.8771513
Yuhang Zhang, Guanghui He, K. Tang, Guoxing Wang
The cross-point memristor array is viewed as a promising candidate for neuromorphic computing due to its non-volatile storage and parallel computing features. However, the programming threshold and resistance fluctuation among different multilevel states restrict the capacity of weight representation and thus numerical precision. This poses great challenges for on-chip learning. This work evaluates the deterioration of learning accuracy on multilayer perceptron due to limited multilevel states and proposes stochastic “skip-and-update” algorithm to facilitate on-chip learning with low-precision memristors.
{"title":"On-chip Learning of Multilayer Perceptron Based on Memristors with Limited Multilevel States","authors":"Yuhang Zhang, Guanghui He, K. Tang, Guoxing Wang","doi":"10.1109/AICAS.2019.8771513","DOIUrl":"https://doi.org/10.1109/AICAS.2019.8771513","url":null,"abstract":"The cross-point memristor array is viewed as a promising candidate for neuromorphic computing due to its non-volatile storage and parallel computing features. However, the programming threshold and resistance fluctuation among different multilevel states restrict the capacity of weight representation and thus numerical precision. This poses great challenges for on-chip learning. This work evaluates the deterioration of learning accuracy on multilayer perceptron due to limited multilevel states and proposes stochastic “skip-and-update” algorithm to facilitate on-chip learning with low-precision memristors.","PeriodicalId":273095,"journal":{"name":"2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133715420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This study proposes an artificial intelligence of things (AIoT) system for electrocardiogram (ECG) analysis and cardiac disease detection. The system includes a front-end IoT-based hardware, a user interface on smart device’s application (APP), a cloud database, and an AI platform for cardiac disease detection. The front-end IoT-based hardware, a wearable ECG patch that includes an analog front-end circuit and a Bluetooth module, can detect ECG signals. The APP on smart devices can not only display users’ real-time ECG signals but also label unusual signals instantly and reach real-time disease detection. These ECG signals will be uploaded to the cloud database. The cloud database is used to store each user’s ECG signals, which forms a big-data database for AI algorithm to detect cardiac disease. The algorithm proposed by this study is based on convolutional neural network and the average accuracy is 94.96%. The ECG dataset applied in this study is collected from patients in Tainan Hospital, Ministry of Health and Welfare. Moreover, signal verification was also performed by a cardiologist.
{"title":"Artificial Intelligence of Things Wearable System for Cardiac Disease Detection","authors":"Yu-Jin Lin, Chen-Wei Chuang, Chun-Yueh Yen, Sheng-Hsin Huang, Peng-Wei Huang, Ju-Yi Chen, Shuenn-Yuh Lee","doi":"10.1109/AICAS.2019.8771630","DOIUrl":"https://doi.org/10.1109/AICAS.2019.8771630","url":null,"abstract":"This study proposes an artificial intelligence of things (AIoT) system for electrocardiogram (ECG) analysis and cardiac disease detection. The system includes a front-end IoT-based hardware, a user interface on smart device’s application (APP), a cloud database, and an AI platform for cardiac disease detection. The front-end IoT-based hardware, a wearable ECG patch that includes an analog front-end circuit and a Bluetooth module, can detect ECG signals. The APP on smart devices can not only display users’ real-time ECG signals but also label unusual signals instantly and reach real-time disease detection. These ECG signals will be uploaded to the cloud database. The cloud database is used to store each user’s ECG signals, which forms a big-data database for AI algorithm to detect cardiac disease. The algorithm proposed by this study is based on convolutional neural network and the average accuracy is 94.96%. The ECG dataset applied in this study is collected from patients in Tainan Hospital, Ministry of Health and Welfare. Moreover, signal verification was also performed by a cardiologist.","PeriodicalId":273095,"journal":{"name":"2019 IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114342928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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