芯片分区辅助:VLSI中可分区性和可测试性的设计技术

21st Design Automation Conference Proceedings Pub Date : 1984-06-25 DOI:10.1109/DAC.1984.1585795

S. DasGupta, M. Graf, R. A. Rasmussen, R. Walther, T. Williams

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引用次数: 7

摘要

本文提出了一种可集成到芯片设计中的结构化分区技术。它打破了测试模式生成成本作为封装中芯片数量的函数呈指数增长的模式。在其中一种形式中，它还具有并行芯片测试的前景，以及将芯片级测试迁移到更高的封装级别进行测试。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Chip Partitioning Aid: A Design Technique for Partitionability and Testability in VLSI

This paper presents a structured partitioning technique which can be integrated into the design of a chip. It breaks the pattern of exponential growth in test pattern generation cost as a function of the number of chips in a package. In one of its forms, it also holds the promise of parallel chip testing, as well as migration of chip-level tests for testing at higher package levels.

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21st Design Automation Conference Proceedings

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