A 21.8-41.6GHz Fast-Locking Sub-Sampling PLL with Dead Zone Automatic Controller Achieving 62.7-fs Jitter and −250.3dB FoM

In this paper, a wideband fast-locking millimeter-wave (mmW) sub-sampling PLL (SSPLL) with low jitter is proposed. A quadrature sub-sampling phase detector (QSSPD)-based dead zone automatic controller (DZAC) is introduced to automatically switch on the frequency-locked loop (FLL) for fast-locking. Here, the long locking time caused by the dead zone of FLL is eliminated. The mmW quad-mode oscillator is integrated in the SSPLL to achieve the low jitter within a wide frequency range. The proposed SSPLL is fabricated in a 40-nm CMOS technology. Measurements exhibit a frequency tuning range of 62.5% from 21.8 to 41.6GHz. The SSPLL achieves a 62.7 to 79.1fs rms jitter within the frequency tuning range. Besides, the typical power consumption is 23.6mW, leading to a PLL FoM of −248.3 to −250.3dB. Meanwhile, the proposed SSPLL achieves more than $8.9\times$ locking time improvement. The PLL occupies a core area of $0.18\text{mm}^{2}$.