{"title":"内存测试地址生成的改进灰色序列和计数器序列","authors":"S. Yarmolik, V. Yarmolik","doi":"10.1109/MIXDES.2006.1706645","DOIUrl":null,"url":null,"abstract":"The goal of this paper is to propose the new techniques for memory test address generation for pattern sensitive faults detection. It has been shown that the previous results based on the multiple runs memory testing are very efficient only for the first iterations. To achieve the high fault coverage the different types of modification have to be used. Two kind of memory address transformation have been proposed, analysed and experimentally validated","PeriodicalId":318768,"journal":{"name":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","volume":"159 8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-06-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"17","resultStr":"{\"title\":\"Modified Gray And Counter Sequences For Memory Test Address Generation\",\"authors\":\"S. Yarmolik, V. Yarmolik\",\"doi\":\"10.1109/MIXDES.2006.1706645\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The goal of this paper is to propose the new techniques for memory test address generation for pattern sensitive faults detection. It has been shown that the previous results based on the multiple runs memory testing are very efficient only for the first iterations. To achieve the high fault coverage the different types of modification have to be used. Two kind of memory address transformation have been proposed, analysed and experimentally validated\",\"PeriodicalId\":318768,\"journal\":{\"name\":\"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.\",\"volume\":\"159 8 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-06-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"17\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MIXDES.2006.1706645\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MIXDES.2006.1706645","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Modified Gray And Counter Sequences For Memory Test Address Generation
The goal of this paper is to propose the new techniques for memory test address generation for pattern sensitive faults detection. It has been shown that the previous results based on the multiple runs memory testing are very efficient only for the first iterations. To achieve the high fault coverage the different types of modification have to be used. Two kind of memory address transformation have been proposed, analysed and experimentally validated
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