40纳米CMOS工艺中输入晶体管的有源ESD保护

VLSI Design, Automation and Test(VLSI-DAT) Pub Date : 2015-04-27 DOI:10.1109/VLSI-DAT.2015.7114533

F. Altolaguirre, M. Ker

{"title":"40纳米CMOS工艺中输入晶体管的有源ESD保护","authors":"F. Altolaguirre, M. Ker","doi":"10.1109/VLSI-DAT.2015.7114533","DOIUrl":null,"url":null,"abstract":"This work presents a novel design for input ESD protection. By replacing the protection resistor with an active switch that isolates the input transistors from the pad under ESD stress, the ESD robustness can be greatly improved. The proposed designs were designed and verified in a 40-nm CMOS process using only thin oxide devices, which can successfully pass the typical industry ESD-protection specifications of 2-kV HBM and 200-V MM ESD tests.","PeriodicalId":369130,"journal":{"name":"VLSI Design, Automation and Test(VLSI-DAT)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-04-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Active ESD protection for input transistors in a 40-nm CMOS process\",\"authors\":\"F. Altolaguirre, M. Ker\",\"doi\":\"10.1109/VLSI-DAT.2015.7114533\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work presents a novel design for input ESD protection. By replacing the protection resistor with an active switch that isolates the input transistors from the pad under ESD stress, the ESD robustness can be greatly improved. The proposed designs were designed and verified in a 40-nm CMOS process using only thin oxide devices, which can successfully pass the typical industry ESD-protection specifications of 2-kV HBM and 200-V MM ESD tests.\",\"PeriodicalId\":369130,\"journal\":{\"name\":\"VLSI Design, Automation and Test(VLSI-DAT)\",\"volume\":\"49 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-04-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"VLSI Design, Automation and Test(VLSI-DAT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSI-DAT.2015.7114533\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"VLSI Design, Automation and Test(VLSI-DAT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI-DAT.2015.7114533","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 4

摘要

本文提出了一种新颖的输入ESD保护设计。通过将保护电阻器替换为主动开关，在ESD应力下隔离输入晶体管和焊盘，可以大大提高ESD稳健性。在40纳米CMOS工艺中，仅使用薄氧化物器件对所提出的设计进行了设计和验证，并成功通过了2 kv HBM和200 v MM典型工业ESD保护规范的ESD测试。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Active ESD protection for input transistors in a 40-nm CMOS process

This work presents a novel design for input ESD protection. By replacing the protection resistor with an active switch that isolates the input transistors from the pad under ESD stress, the ESD robustness can be greatly improved. The proposed designs were designed and verified in a 40-nm CMOS process using only thin oxide devices, which can successfully pass the typical industry ESD-protection specifications of 2-kV HBM and 200-V MM ESD tests.

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VLSI Design, Automation and Test(VLSI-DAT)

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