Low Power, Low Offset, Area Efficient Comparator Design in Nanoscale CMOS Technology

Low power, area efficient clocked comparator with high resolution was designed in SAED 32/28nm CMOS process for SAR ADC applications. The analog comparator is based on digital cells, hence doesn't have stability issues, mismatches induced by the differential pair, can be easily integrated to the digital part of VLSI systems, dissipates small power, and has a small area. Input offset equation of the comparator was derived considering mismatches between transfer characteristics of the comparator stages and calculated total offset with Monte-Carlo simulation. Finally, the comparator performance was verified over PVT variation in designed 10-bit SAR ADC.