{"title":"CalmlRISC32浮点单元的设计与实现","authors":"C. Jeong, W. Park, Sang-Woo Kim, T. Han","doi":"10.1109/APASIC.2000.896974","DOIUrl":null,"url":null,"abstract":"The CalmRISC32 FPU is RISC style coprocessor for embedded systems. It supports IEEE-754 standard single precision addition/subtraction, floating-point multiplication, floating-point division, format conversion, comparison, rounding, and load/store. It also supports four rounding modes, and precise exception. It can execute and complete instructions out of order if some constraint is resolved-data dependency, resource conflict, and exception prediction. Standard cell base design technique is used to save design time and cost. First prototype is running at about 70 Mhz with worst-case delay in gate level simulation.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"109 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"The design and implementation of CalmlRISC32 floating point unit\",\"authors\":\"C. Jeong, W. Park, Sang-Woo Kim, T. Han\",\"doi\":\"10.1109/APASIC.2000.896974\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The CalmRISC32 FPU is RISC style coprocessor for embedded systems. It supports IEEE-754 standard single precision addition/subtraction, floating-point multiplication, floating-point division, format conversion, comparison, rounding, and load/store. It also supports four rounding modes, and precise exception. It can execute and complete instructions out of order if some constraint is resolved-data dependency, resource conflict, and exception prediction. Standard cell base design technique is used to save design time and cost. First prototype is running at about 70 Mhz with worst-case delay in gate level simulation.\",\"PeriodicalId\":313978,\"journal\":{\"name\":\"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)\",\"volume\":\"109 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-08-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APASIC.2000.896974\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APASIC.2000.896974","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The design and implementation of CalmlRISC32 floating point unit
The CalmRISC32 FPU is RISC style coprocessor for embedded systems. It supports IEEE-754 standard single precision addition/subtraction, floating-point multiplication, floating-point division, format conversion, comparison, rounding, and load/store. It also supports four rounding modes, and precise exception. It can execute and complete instructions out of order if some constraint is resolved-data dependency, resource conflict, and exception prediction. Standard cell base design technique is used to save design time and cost. First prototype is running at about 70 Mhz with worst-case delay in gate level simulation.