An improved cost heuristic for transistor sizing

An improved cost heuristic for selecting the transistor to size on the worst-delay path in a CMOS circuit is presented. Traditional cost heuristics used in a TILOS-like approach assume a single dominant critical path, ignoring the interactions among different paths in a circuit. As a result, layouts with larger than necessary active area are produced when the delay constraints are tight. Convex programming based approaches produce layouts with near-optimal area but at the cost of prohibitively long running times. The improved cost heuristic presented in this work takes into account the effect of sizing a given transistor T on many different critical paths in the circuit, based on local information in the neighborhood of T. When used with a TILOS-like algorithm, the heuristic produces layouts with considerably lower active area than layouts generated using the traditional cost heuristics. Moreover the number of iterations required using the improved heuristic is smaller than with the traditional cost heuristic resulting in lower CPU time requirement.