T. Dickson, Z. Deniz, M. Cochet, M. Kossel, T. Morf, Young-Ho Choi, P. Francese, M. Brändli, T. Beukema, C. Baks, J. Proesel, J. Bulzacchelli, Michael P. Beakes, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, M. Meghelli, Hyo-Gyuem Rhew, D. Friedman, Michael Choi, M. Soyuer, Jongshin Shin
{"title":"72GS/s, 8位基于dac的有线发射机，4nm FinFET CMOS，用于200+Gb/s串行链路","authors":"T. Dickson, Z. Deniz, M. Cochet, M. Kossel, T. Morf, Young-Ho Choi, P. Francese, M. Brändli, T. Beukema, C. Baks, J. Proesel, J. Bulzacchelli, Michael P. Beakes, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, M. Meghelli, Hyo-Gyuem Rhew, D. Friedman, Michael Choi, M. Soyuer, Jongshin Shin","doi":"10.1109/vlsitechnologyandcir46769.2022.9830421","DOIUrl":null,"url":null,"abstract":"A DAC-based SST transmitter for wireline applications is reported in a 4nm FinFET technology. 8b resolution and high analog output bandwidth (BW) are achieved by employing a segmented architecture along with a single-ended LSB. Hybrid analog/digital tuning is used in the DAC LSB segments, resulting in well-matched MSB/LSB segments with -0.63/0.67 LSB INL and -0.16/0.43 LSB DNL. 216Gb/s PAM8 and 212Gb/s QAM64 OFDM operation are demonstrated at 288mW from a 0.95V supply.","PeriodicalId":332454,"journal":{"name":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2022-06-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links\",\"authors\":\"T. Dickson, Z. Deniz, M. Cochet, M. Kossel, T. Morf, Young-Ho Choi, P. Francese, M. Brändli, T. Beukema, C. Baks, J. Proesel, J. Bulzacchelli, Michael P. Beakes, Byoung-Joo Yoo, Hyoungbae Ahn, Dong-Hyuk Lim, Gunil Kang, Sang-Hune Park, M. Meghelli, Hyo-Gyuem Rhew, D. Friedman, Michael Choi, M. Soyuer, Jongshin Shin\",\"doi\":\"10.1109/vlsitechnologyandcir46769.2022.9830421\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A DAC-based SST transmitter for wireline applications is reported in a 4nm FinFET technology. 8b resolution and high analog output bandwidth (BW) are achieved by employing a segmented architecture along with a single-ended LSB. Hybrid analog/digital tuning is used in the DAC LSB segments, resulting in well-matched MSB/LSB segments with -0.63/0.67 LSB INL and -0.16/0.43 LSB DNL. 216Gb/s PAM8 and 212Gb/s QAM64 OFDM operation are demonstrated at 288mW from a 0.95V supply.\",\"PeriodicalId\":332454,\"journal\":{\"name\":\"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-06-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830421\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830421","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 72GS/s, 8-bit DAC-based Wireline Transmitter in 4nm FinFET CMOS for 200+Gb/s Serial Links
A DAC-based SST transmitter for wireline applications is reported in a 4nm FinFET technology. 8b resolution and high analog output bandwidth (BW) are achieved by employing a segmented architecture along with a single-ended LSB. Hybrid analog/digital tuning is used in the DAC LSB segments, resulting in well-matched MSB/LSB segments with -0.63/0.67 LSB INL and -0.16/0.43 LSB DNL. 216Gb/s PAM8 and 212Gb/s QAM64 OFDM operation are demonstrated at 288mW from a 0.95V supply.
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