模拟测试覆盖的框架

D. Bhatta, I. Mukhopadhyay, S. Natarajan, P. Goteti, Bin Xue
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引用次数: 9

摘要

在微处理器的大批量生产过程中,测试质量的测量对于确保期望的输出产品质量非常重要。对于芯片上的数字逻辑,这种测量是使用快速事件驱动故障模拟等技术来执行的,这些技术使用成熟的故障模型,如卡滞故障和过渡故障。对于模具上的模拟模块,由于缺乏(a)成熟的故障模型来描述模拟故障,以及(b)自动化、高效和准确的故障模拟方法,因此在实践中没有进行这种测试质量测量。这项工作是我们建立一种实用的方法来测量模拟测试质量的目标的第一步。我们在高速串行IO接收器的模拟模块上展示了半自动故障模拟方法的有希望的结果,该方法比较了(a)两种制造测试的缺陷检测能力,这是由它们对总故障和参数故障的故障覆盖率来衡量的,以及(b)使用模型与原理图进行故障影响传播的准确性和性能。
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Framework for analog test coverage
Measurement of the quality of tests run during high volume manufacturing of microprocessors is important to ensure desired outgoing product quality. For digital logic on die, such measurement is performed using techniques such as fast event-driven fault simulation using mature fault models such as stuck-at and transition faults. For analog modules on die, such test quality measurement is not performed in practice due to lack of (a) mature fault models to describe analog failures, and (b) automated, efficient and accurate fault simulation methods. This work is a first step towards our objective of establishing a practical methodology to measure analog test quality. We show promising results of a semi-automated fault simulation approach on analog modules of a high speed serial IO receiver that compares (a) two manufacturing tests in terms of their defect detection capability as measured by their fault coverages for gross and parametric faults, and, (b) the accuracy and performance of using models versus schematics for fault effect propagation.
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