Frequency synthesizer architectural design for digital radar testbed

This paper presents the design of a Phase Locked Loop (PLL) system and frequency synthesizer for an architecture that aims to miniaturize a digital radar test bed implemented using discrete microwave components. The designed PLL architecture acts as a frequency synthesizer to provide three distinct frequencies of 800 MHz, 2.0 GHz, and 2.4 GHz to the respective chips of the digital radar system. Full frequency plan and spurs analysis have been conducted. The outcome shows that it is best to implement the frequency synthesizer off the chip where the main transceiver is being developed. This ensures both full synchronization of the transmitter and receivers as well as reduced on-chip interference. Each component of the PLL system is individually designed using a suitable simulation program. The components are then combined to provide the overall PLL system delivering the desired frequencies.