{"title":"基于单板计算机和FPGA协同设计的图像处理算法加速","authors":"Petros Kokotis, J. Vourvoulakis","doi":"10.1109/mocast54814.2022.9837774","DOIUrl":null,"url":null,"abstract":"During recent years, various hardware platforms were developed, each one suitable for use in different kind of applications. Platforms based on FPGAs, DSPs, GPUs, Single Board Computers, microcontrollers extend processing capabilities and functionality in comparison with traditional personal computers based on a single CPU. Furthermore, co-design combines advantages from different types of processing units, rendering such architectures more attractive to researchers. In this paper, we achieve acceleration of image processing algorithms using a hardware platform based on a Raspberry Pi Single Board Computer and a custom designed FPGA HAT (Hardware Attached on Top) for RPi. The FPGA HAT consists of a Cyclone 10LP device. The FPGA undertakes a computationally demanding load, such as robotic vision algorithms exploiting parallelism, while the RPi can apply higher level operations such as running ROS (Robot Operating System). In order to overcome bottleneck in exchanging data between RPi and FPGA, a 16-bit parallel customized protocol was developed from scratch. The achieved transfer rate was about 50 Mbytes/sec when multi threaded software was implemented for the RPi. An image edge detector was implemented in order to verify the system performance. When only the RPi was used, the processing rate was 48fps for images with resolution 512x512 pixels. RPi and FPGA co-design achieved processing rate 170fps for the same resolution images, which means an acceleration of about 350%. The proposed system was also evaluated in terms of power consumption.","PeriodicalId":122414,"journal":{"name":"2022 11th International Conference on Modern Circuits and Systems Technologies (MOCAST)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Acceleration of image processing algorithms based on a Single Board Computer and FPGA co-design\",\"authors\":\"Petros Kokotis, J. Vourvoulakis\",\"doi\":\"10.1109/mocast54814.2022.9837774\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"During recent years, various hardware platforms were developed, each one suitable for use in different kind of applications. Platforms based on FPGAs, DSPs, GPUs, Single Board Computers, microcontrollers extend processing capabilities and functionality in comparison with traditional personal computers based on a single CPU. Furthermore, co-design combines advantages from different types of processing units, rendering such architectures more attractive to researchers. In this paper, we achieve acceleration of image processing algorithms using a hardware platform based on a Raspberry Pi Single Board Computer and a custom designed FPGA HAT (Hardware Attached on Top) for RPi. The FPGA HAT consists of a Cyclone 10LP device. The FPGA undertakes a computationally demanding load, such as robotic vision algorithms exploiting parallelism, while the RPi can apply higher level operations such as running ROS (Robot Operating System). In order to overcome bottleneck in exchanging data between RPi and FPGA, a 16-bit parallel customized protocol was developed from scratch. The achieved transfer rate was about 50 Mbytes/sec when multi threaded software was implemented for the RPi. An image edge detector was implemented in order to verify the system performance. When only the RPi was used, the processing rate was 48fps for images with resolution 512x512 pixels. RPi and FPGA co-design achieved processing rate 170fps for the same resolution images, which means an acceleration of about 350%. The proposed system was also evaluated in terms of power consumption.\",\"PeriodicalId\":122414,\"journal\":{\"name\":\"2022 11th International Conference on Modern Circuits and Systems Technologies (MOCAST)\",\"volume\":\"32 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-06-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 11th International Conference on Modern Circuits and Systems Technologies (MOCAST)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/mocast54814.2022.9837774\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 11th International Conference on Modern Circuits and Systems Technologies (MOCAST)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/mocast54814.2022.9837774","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Acceleration of image processing algorithms based on a Single Board Computer and FPGA co-design
During recent years, various hardware platforms were developed, each one suitable for use in different kind of applications. Platforms based on FPGAs, DSPs, GPUs, Single Board Computers, microcontrollers extend processing capabilities and functionality in comparison with traditional personal computers based on a single CPU. Furthermore, co-design combines advantages from different types of processing units, rendering such architectures more attractive to researchers. In this paper, we achieve acceleration of image processing algorithms using a hardware platform based on a Raspberry Pi Single Board Computer and a custom designed FPGA HAT (Hardware Attached on Top) for RPi. The FPGA HAT consists of a Cyclone 10LP device. The FPGA undertakes a computationally demanding load, such as robotic vision algorithms exploiting parallelism, while the RPi can apply higher level operations such as running ROS (Robot Operating System). In order to overcome bottleneck in exchanging data between RPi and FPGA, a 16-bit parallel customized protocol was developed from scratch. The achieved transfer rate was about 50 Mbytes/sec when multi threaded software was implemented for the RPi. An image edge detector was implemented in order to verify the system performance. When only the RPi was used, the processing rate was 48fps for images with resolution 512x512 pixels. RPi and FPGA co-design achieved processing rate 170fps for the same resolution images, which means an acceleration of about 350%. The proposed system was also evaluated in terms of power consumption.