{"title":"InP (111)A表面上NMOSFET的“零”漏极电流漂移","authors":"Chen Wang, Min Xu, R. Colby, E. Stach, P. Ye","doi":"10.1109/DRC.2011.5994430","DOIUrl":null,"url":null,"abstract":"InP is a commonly used compound semiconductor with wide applications in electronic, optoelectronic, and photonic devices. Compared to GaAs, InP is widely believed to be a more forgiving material with respect to Fermi level pinning and has a higher electron saturation velocity (2.5×107 cm/s) as well. It could be a viable channel material for high-speed logic applications if a high-quality, thermodynamically stable high-k dielectric could be found. [1] It is of great importance for the understanding of high-k/InP interfaces since InP is identified as a transition layer for ALD high-k/InGaAs quantum well transistor in state-of-the-art devices. [2] Motivated by previous work on surface orientation studies of GaAs [3] and InGaAs [4], we have systematically studied NMOSFETs, MOSCAPs, and interfacial chemistry on two different crystalline surfaces: InP (100) and (111)A (In-rich). With ALD Al2O3 in direct contact as gate dielectric, a record high drain current of 600 µA/µm is obtained for an InP inversion-mode MOSFET on the (111)A surface with a gate length of 1µm, which is a factor of 2.6 enhancement compared to the (100) surface at the same VG-VT condition. The smoother Al2O3/(111)A interface and a shift of the charge-neutrality-level (CNL) [5] on InP(111)A toward the conduction band edge is identified as the origin of this drain current enhancement in spite of the extracted interface trap density (Dit). [6] In this paper, we report on “zero” drain-current drift on InP (111)A MOSFETs which is a major issue to prevent commercializing InP MOSFET technology on (100) surface in 1980s. [7]","PeriodicalId":107059,"journal":{"name":"69th Device Research Conference","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2011-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"“Zero” drain-current drift of inversion-mode NMOSFET on InP (111)A surface\",\"authors\":\"Chen Wang, Min Xu, R. Colby, E. Stach, P. Ye\",\"doi\":\"10.1109/DRC.2011.5994430\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"InP is a commonly used compound semiconductor with wide applications in electronic, optoelectronic, and photonic devices. Compared to GaAs, InP is widely believed to be a more forgiving material with respect to Fermi level pinning and has a higher electron saturation velocity (2.5×107 cm/s) as well. It could be a viable channel material for high-speed logic applications if a high-quality, thermodynamically stable high-k dielectric could be found. [1] It is of great importance for the understanding of high-k/InP interfaces since InP is identified as a transition layer for ALD high-k/InGaAs quantum well transistor in state-of-the-art devices. [2] Motivated by previous work on surface orientation studies of GaAs [3] and InGaAs [4], we have systematically studied NMOSFETs, MOSCAPs, and interfacial chemistry on two different crystalline surfaces: InP (100) and (111)A (In-rich). With ALD Al2O3 in direct contact as gate dielectric, a record high drain current of 600 µA/µm is obtained for an InP inversion-mode MOSFET on the (111)A surface with a gate length of 1µm, which is a factor of 2.6 enhancement compared to the (100) surface at the same VG-VT condition. The smoother Al2O3/(111)A interface and a shift of the charge-neutrality-level (CNL) [5] on InP(111)A toward the conduction band edge is identified as the origin of this drain current enhancement in spite of the extracted interface trap density (Dit). [6] In this paper, we report on “zero” drain-current drift on InP (111)A MOSFETs which is a major issue to prevent commercializing InP MOSFET technology on (100) surface in 1980s. [7]\",\"PeriodicalId\":107059,\"journal\":{\"name\":\"69th Device Research Conference\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-06-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"69th Device Research Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DRC.2011.5994430\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"69th Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC.2011.5994430","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
“Zero” drain-current drift of inversion-mode NMOSFET on InP (111)A surface
InP is a commonly used compound semiconductor with wide applications in electronic, optoelectronic, and photonic devices. Compared to GaAs, InP is widely believed to be a more forgiving material with respect to Fermi level pinning and has a higher electron saturation velocity (2.5×107 cm/s) as well. It could be a viable channel material for high-speed logic applications if a high-quality, thermodynamically stable high-k dielectric could be found. [1] It is of great importance for the understanding of high-k/InP interfaces since InP is identified as a transition layer for ALD high-k/InGaAs quantum well transistor in state-of-the-art devices. [2] Motivated by previous work on surface orientation studies of GaAs [3] and InGaAs [4], we have systematically studied NMOSFETs, MOSCAPs, and interfacial chemistry on two different crystalline surfaces: InP (100) and (111)A (In-rich). With ALD Al2O3 in direct contact as gate dielectric, a record high drain current of 600 µA/µm is obtained for an InP inversion-mode MOSFET on the (111)A surface with a gate length of 1µm, which is a factor of 2.6 enhancement compared to the (100) surface at the same VG-VT condition. The smoother Al2O3/(111)A interface and a shift of the charge-neutrality-level (CNL) [5] on InP(111)A toward the conduction band edge is identified as the origin of this drain current enhancement in spite of the extracted interface trap density (Dit). [6] In this paper, we report on “zero” drain-current drift on InP (111)A MOSFETs which is a major issue to prevent commercializing InP MOSFET technology on (100) surface in 1980s. [7]