{"title":"一个CMOS三阶ΔΣ调制器与基于逆变器的积分器","authors":"Jeong H. Choi, K. Yoon","doi":"10.1109/SOCC.2017.8226025","DOIUrl":null,"url":null,"abstract":"This paper presents a CMOS third order ΔΣ modulator with inverter-based integrators for low power audio signal processing application. In order to minimize the power consumption of the proposed modulator, the inverters embedded into integrators and an analog adder operating in the subthreshold region were implemented on an 180nm CMOS technology with digital and analog power supply of 1.8V and 0.8V, respectively. The measurement results demonstrated ENOB of 13.1bit, DR of 86.1dB, total power dissipation of 92uW, and FOM(walden) of 260 fJ/step at sampling frequency of 2.56 MHz and input signal frequency of 2.5kHz.","PeriodicalId":366264,"journal":{"name":"2017 30th IEEE International System-on-Chip Conference (SOCC)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A CMOS third order ΔΣ modulator with inverter-based integrators\",\"authors\":\"Jeong H. Choi, K. Yoon\",\"doi\":\"10.1109/SOCC.2017.8226025\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a CMOS third order ΔΣ modulator with inverter-based integrators for low power audio signal processing application. In order to minimize the power consumption of the proposed modulator, the inverters embedded into integrators and an analog adder operating in the subthreshold region were implemented on an 180nm CMOS technology with digital and analog power supply of 1.8V and 0.8V, respectively. The measurement results demonstrated ENOB of 13.1bit, DR of 86.1dB, total power dissipation of 92uW, and FOM(walden) of 260 fJ/step at sampling frequency of 2.56 MHz and input signal frequency of 2.5kHz.\",\"PeriodicalId\":366264,\"journal\":{\"name\":\"2017 30th IEEE International System-on-Chip Conference (SOCC)\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 30th IEEE International System-on-Chip Conference (SOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCC.2017.8226025\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 30th IEEE International System-on-Chip Conference (SOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCC.2017.8226025","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A CMOS third order ΔΣ modulator with inverter-based integrators
This paper presents a CMOS third order ΔΣ modulator with inverter-based integrators for low power audio signal processing application. In order to minimize the power consumption of the proposed modulator, the inverters embedded into integrators and an analog adder operating in the subthreshold region were implemented on an 180nm CMOS technology with digital and analog power supply of 1.8V and 0.8V, respectively. The measurement results demonstrated ENOB of 13.1bit, DR of 86.1dB, total power dissipation of 92uW, and FOM(walden) of 260 fJ/step at sampling frequency of 2.56 MHz and input signal frequency of 2.5kHz.
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