增量测试模式生成

Sang-Hoon Song, L. Kinney
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引用次数: 1

摘要

讨论了组合逻辑电路中单卡故障的测试模式生成算法。目前的TPG系统独立于先前对故障F/sub 1/、F/sub 2/、…、F/sub i/进行的计算,为故障F/sub i+1/生成测试向量。ITPG算法从(继承)故障F/sub i/的测试向量开始,生成故障F/sub i+1/的测试向量。通过逐渐改变继承值来生成新的测试向量。所继承的值可以部分地激活故障并传播故障信号。通常,这减少了第二次搜索中的决策步骤和回溯的数量。对知名基准电路的实验结果表明,ITPG具有很高的效率和较小的回溯限制;与其他算法相结合,它对任意回溯限制非常有效。
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Incremental test pattern generation
Discusses a test pattern generation (TPG) algorithm for single stuck-at faults in combinational logic circuits. Current TPG systems generate a test vector for fault F/sub i+1/ independently of the computation previously done for faults F/sub 1/, F/sub 2/, . . ., F/sub i/. The algorithm ITPG, generates a test vector for fault F/sub i+1/ by starting with (inheriting) the test vector for fault F/sub i/. A new test vector is generated from inherited values by gradually changing the inherited values. The inherited values may partially activate a fault and propagate the fault signal. Normally, this reduces the number of decision steps and backtracks in the second search. Experimental results for well-known benchmark circuits show that ITPG is very efficient with a small backtrack limit; in combination with other algorithms, it is very efficient for arbitrary backtrack limits.<>
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