Y. Takai, M. Nagase, Mamoru Kitamura, Yasuji Koshikawa, Naoyuki Yoshida, Yasuaki Kobayashi, Takashi Obara, Y. Fukuzo, H. Watanabe
{"title":"采用三级流水线架构的250兆字节/秒同步DRAM","authors":"Y. Takai, M. Nagase, Mamoru Kitamura, Yasuji Koshikawa, Naoyuki Yoshida, Yasuaki Kobayashi, Takashi Obara, Y. Fukuzo, H. Watanabe","doi":"10.1109/VLSIC.1993.920536","DOIUrl":null,"url":null,"abstract":"A 3.3 V 512 k/spl times/18/spl times/2 bank synchronous DRAM has been developed using a novel 3-stage-pipelined architecture. The address-access path which is usually designed by analog means, is digitized, separated into three stages by latch circuits at the column switch and data-out buffer. Since this architecture requires no additional read/write bus and data amp, it minimizes an increase in die size. Using the standardized GTL interface, a 250 Mbyte/sec synchronous DRAM with almost the same die-size as the conventional DRAM has been achieved.","PeriodicalId":127467,"journal":{"name":"Symposium 1993 on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"35","resultStr":"{\"title\":\"250 Mbyte/sec synchronous DRAM using a 3-stage-pipelined architecture\",\"authors\":\"Y. Takai, M. Nagase, Mamoru Kitamura, Yasuji Koshikawa, Naoyuki Yoshida, Yasuaki Kobayashi, Takashi Obara, Y. Fukuzo, H. Watanabe\",\"doi\":\"10.1109/VLSIC.1993.920536\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 3.3 V 512 k/spl times/18/spl times/2 bank synchronous DRAM has been developed using a novel 3-stage-pipelined architecture. The address-access path which is usually designed by analog means, is digitized, separated into three stages by latch circuits at the column switch and data-out buffer. Since this architecture requires no additional read/write bus and data amp, it minimizes an increase in die size. Using the standardized GTL interface, a 250 Mbyte/sec synchronous DRAM with almost the same die-size as the conventional DRAM has been achieved.\",\"PeriodicalId\":127467,\"journal\":{\"name\":\"Symposium 1993 on VLSI Circuits\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-05-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"35\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Symposium 1993 on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.1993.920536\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Symposium 1993 on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1993.920536","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 35
摘要
3.3 V 512 k/spl倍/18/spl倍/2组同步DRAM采用新颖的3级流水线架构。通常采用模拟方式设计的地址访问路径经过数字化处理，通过列开关和数据输出缓冲器处的锁存电路将其分为三级。由于这种架构不需要额外的读/写总线和数据放大器，它最大限度地减少了芯片尺寸的增加。使用标准化的GTL接口，实现了250 Mbyte/s的同步DRAM，其芯片尺寸几乎与传统DRAM相同。
250 Mbyte/sec synchronous DRAM using a 3-stage-pipelined architecture
A 3.3 V 512 k/spl times/18/spl times/2 bank synchronous DRAM has been developed using a novel 3-stage-pipelined architecture. The address-access path which is usually designed by analog means, is digitized, separated into three stages by latch circuits at the column switch and data-out buffer. Since this architecture requires no additional read/write bus and data amp, it minimizes an increase in die size. Using the standardized GTL interface, a 250 Mbyte/sec synchronous DRAM with almost the same die-size as the conventional DRAM has been achieved.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
