利用双端口网络模型分析攻击者和受害者互连之间的串扰耦合效应

A. K. Palit, V. Meyer, W. Anheier, J. Schloeffel
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引用次数: 3

摘要

A. Attartha和M. Nourani(2002)指出,互连中的信号完整性(SI)损耗是高频工作时寄生电容、电阻和电感的分布特性所产生的干扰。如果多个互连线相互耦合能量,则SI损耗会进一步加剧。因此,本文旨在利用ABCD双端口网络模型分析攻击线和受害线这两条互连线之间的串扰耦合效应。为了减少仿真时间,考虑对互连线进行降阶建模。此外,正如a . Sinha等人(1999)在各种文献中所述,由简单阶跃函数表示的上升(或下降)输入信号不够准确,因此本文使用指数项更准确地表示上升跃迁和下降跃迁,并基于这种输入表示来确定存在串扰噪声的时域输出信号电压,在攻击线和受害线的远端。这样的输出电压表示在估计延迟、超调或欠调等方面非常有帮助,这些被认为会导致SoC中的SI损耗。
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Analysis of crosstalk coupling effects between aggressor and victim interconnect using two-port network model
Signal integrity (SI) losses in the interconnects are the disturbances coming out of their distributed nature of parasitic capacitances, resistances, and inductances at high frequency operation by A. Attartha and M. Nourani (2002). SI losses are further aggravated if multiple interconnect lines couple energy from, or to each other. Therefore, this paper aims to analyze the cross-talk coupling effects between the two interconnects, namely the aggressor and victim lines, using the ABCD two-port network model. In order to reduce the simulation time a reduced order modeling of the interconnect line is considered. Furthermore, as stated in various literatures by A. Sinha et al. (1999) the rising (or falling) input signal represented by a simple step function is not accurate enough, therefore in this paper the rising transitions and the falling transitions are represented more accurately using the exponential terms, and based on such input representation the time domain output signal voltage in presence of crosstalk noise, at the far end side of both aggressor line and victim line, is determined. Such output voltage representation is very helpful in estimating the delay, overshoot or undershoot etc., which are believed to cause SI losses in the SoC.
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Presentation of a new time domain simulation tool and application to the analysis of advanced interconnect performance dependence on design and process parameters Sensitivity analysis of generic on-chip /spl Delta/I-noise simulation methodology A frequency domain approach for efficient model reduction of mixed VLSI circuits Non-uniform grid (NG) algorithm for fast capacitance extraction Dampening high frequency noise in high performance microprocessor packaging
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