一个1.8 V全嵌入式10 b 160 MS/s两步ADC在0.18 /spl μ m CMOS

M. Clara, A. Wiesbauer, F. Kuttner
{"title":"一个1.8 V全嵌入式10 b 160 MS/s两步ADC在0.18 /spl μ m CMOS","authors":"M. Clara, A. Wiesbauer, F. Kuttner","doi":"10.1109/CICC.2002.1012868","DOIUrl":null,"url":null,"abstract":"A two-step ADC with interleaved fine conversion achieves 9.1 effective bits with a sampling frequency of 160 MHz. The effective resolution exceeds 8.5 bits for signal frequencies up to 66 MHz. The 10 bit converter with on-chip driver and reference measures only 1 mm/sup 2/ in a standard 0.18 /spl mu/m CMOS process and consumes 190 mW from a single 1.8 V supply. The fully embedded design is targeted at SoC-integration.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":"{\"title\":\"A 1.8 V fully embedded 10 b 160 MS/s two-step ADC in 0.18 /spl mu/m CMOS\",\"authors\":\"M. Clara, A. Wiesbauer, F. Kuttner\",\"doi\":\"10.1109/CICC.2002.1012868\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A two-step ADC with interleaved fine conversion achieves 9.1 effective bits with a sampling frequency of 160 MHz. The effective resolution exceeds 8.5 bits for signal frequencies up to 66 MHz. The 10 bit converter with on-chip driver and reference measures only 1 mm/sup 2/ in a standard 0.18 /spl mu/m CMOS process and consumes 190 mW from a single 1.8 V supply. The fully embedded design is targeted at SoC-integration.\",\"PeriodicalId\":209025,\"journal\":{\"name\":\"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2002.1012868\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2002.1012868","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 14

摘要

采用交错精细转换的两步ADC,采样频率为160 MHz,有效位为9.1位。有效分辨率超过8.5位,信号频率高达66mhz。带有片上驱动器和参考的10位转换器在标准的0.18 /spl mu/m CMOS工艺中仅测量1 mm/sup 2/,单个1.8 V电源消耗190 mW。全嵌入式设计以soc集成为目标。
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A 1.8 V fully embedded 10 b 160 MS/s two-step ADC in 0.18 /spl mu/m CMOS
A two-step ADC with interleaved fine conversion achieves 9.1 effective bits with a sampling frequency of 160 MHz. The effective resolution exceeds 8.5 bits for signal frequencies up to 66 MHz. The 10 bit converter with on-chip driver and reference measures only 1 mm/sup 2/ in a standard 0.18 /spl mu/m CMOS process and consumes 190 mW from a single 1.8 V supply. The fully embedded design is targeted at SoC-integration.
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