一个1.8 V全嵌入式10 b 160 MS/s两步ADC在0.18 /spl μ m CMOS

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285) Pub Date : 2002-08-07 DOI:10.1109/CICC.2002.1012868

M. Clara, A. Wiesbauer, F. Kuttner

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引用次数: 14

摘要

采用交错精细转换的两步ADC，采样频率为160 MHz，有效位为9.1位。有效分辨率超过8.5位，信号频率高达66mhz。带有片上驱动器和参考的10位转换器在标准的0.18 /spl mu/m CMOS工艺中仅测量1 mm/sup 2/，单个1.8 V电源消耗190 mW。全嵌入式设计以soc集成为目标。

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A 1.8 V fully embedded 10 b 160 MS/s two-step ADC in 0.18 /spl mu/m CMOS

A two-step ADC with interleaved fine conversion achieves 9.1 effective bits with a sampling frequency of 160 MHz. The effective resolution exceeds 8.5 bits for signal frequencies up to 66 MHz. The 10 bit converter with on-chip driver and reference measures only 1 mm/sup 2/ in a standard 0.18 /spl mu/m CMOS process and consumes 190 mW from a single 1.8 V supply. The fully embedded design is targeted at SoC-integration.

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Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)

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