{"title":"55ns CMOS EEPROM","authors":"R. Zeman, Chun Ho, T. Chang","doi":"10.1109/ISSCC.1984.1156661","DOIUrl":null,"url":null,"abstract":"A 32,768 (4K×8) CMOS EEPROM with a 55ns address access time will be discussed. Access time through the memory array was accomplished by using two memory cells per bit. A differential signal is generated on complementary bit lines to reduce the voltage swing necessary for sensing.","PeriodicalId":260117,"journal":{"name":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"2 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"A 55ns CMOS EEPROM\",\"authors\":\"R. Zeman, Chun Ho, T. Chang\",\"doi\":\"10.1109/ISSCC.1984.1156661\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 32,768 (4K×8) CMOS EEPROM with a 55ns address access time will be discussed. Access time through the memory array was accomplished by using two memory cells per bit. A differential signal is generated on complementary bit lines to reduce the voltage swing necessary for sensing.\",\"PeriodicalId\":260117,\"journal\":{\"name\":\"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"volume\":\"2 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1984.1156661\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1984.1156661","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 32,768 (4K×8) CMOS EEPROM with a 55ns address access time will be discussed. Access time through the memory array was accomplished by using two memory cells per bit. A differential signal is generated on complementary bit lines to reduce the voltage swing necessary for sensing.
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