Ultra-low power on-chip differential interconnects using high-resolution comparator

A global link architecture is proposed for high-speed, ultra-low-energy communication. A high-resolution comparator at receiver is used to reduce the voltage requirement. At the driver, we adopt a continuous-time linear equalizer (CTLE) with low-voltage differential signaling (LVDS) to save power. Compared with the state-of-art on-chip interconnect driver-receiver co-design, over 75% reduction is observed in energy-per-bit. With dual driver supply of 1.1V and 0.8V, the interconnect runs at 10.0 Gpbs signaling. For top layer wires at 10mm distance using 2.2 μm pitch, we use ground shield on three sides. The communication achieves 21.5ps/mm latency and consumes 0.053pJ/b. For intermediate layer wires at 2.5 mm distance using 0.6 μm pitch, we use ground shield on 4 sides. The communication achieves 55.2 ps/mm latency and 0.048pJ/b energy using the predictive 45nm CMOS model.