Low power multi-chains encoding scheme for SoC in low-cost environment

In this paper, new compression architecture is proposed for multiple scan-chains. We use buffers to hold back data, and use read enable signals to filter useless data. We use only four extra channels (which is less than [1]) and less hardware for largest ISCAS'89 circuits to reduce test data volume and shift-in power. The average of peak/WTC shift-in turns to 3x/6.6x, after comparing [1] and our method. The average of improvement/ hardware is 16%/6%.