用于无线应用的减少混叠的CMOS中频采样电路

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI:10.1109/ISSCC.2002.993103

S. Levantino, C. Samori, M. Banu, Jack Glas, V. Boccuzzi

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引用次数: 4

摘要

中频采样技术拒绝偶阶混叠信道。0.25 /spl μ l /m CMOS测试芯片在377 MHz中频GSM信号、52 MHz采样率下，具有27 dB抗混叠抑制、70 dB动态范围和-121 dBm/Hz底噪声。

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A CMOS IF sampling circuit with reduced aliasing for wireless applications

An IF-sampling technique rejects even-order alias channels. A 0.25 /spl mu/m CMOS test chip demonstrates 27 dB anti-aliasing rejection, 70 dB dynamic range, and -121 dBm/Hz noise floor, for a 377 MHz IF GSM signal, with 52 MHz sampling rate.

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2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

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