{"title":"组合电路冗余结构分析","authors":"E. Isern, J. Figueras","doi":"10.1109/VTEST.1993.313313","DOIUrl":null,"url":null,"abstract":"An efficient method for the analysis and detection of functionally equivalent nodes in combinational circuits is presented. In this work these nodes are called f-redundant nodes. The proposed method consists of two phases: First, a reduced set of pseudorandom input vectors is used to reduce the number of classes of nodes that are candidates for f-redundancy. In the second phase, ordered binary decision diagrams are used to check the equivalences between the logic functions of the remaining f-redundant node candidates. The efficiency of the proposed algorithm has been evaluated on the ISCAS'85 benchmark circuits.<<ETX>>","PeriodicalId":283218,"journal":{"name":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Analysis of redundant structures in combinational circuits\",\"authors\":\"E. Isern, J. Figueras\",\"doi\":\"10.1109/VTEST.1993.313313\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An efficient method for the analysis and detection of functionally equivalent nodes in combinational circuits is presented. In this work these nodes are called f-redundant nodes. The proposed method consists of two phases: First, a reduced set of pseudorandom input vectors is used to reduce the number of classes of nodes that are candidates for f-redundancy. In the second phase, ordered binary decision diagrams are used to check the equivalences between the logic functions of the remaining f-redundant node candidates. The efficiency of the proposed algorithm has been evaluated on the ISCAS'85 benchmark circuits.<<ETX>>\",\"PeriodicalId\":283218,\"journal\":{\"name\":\"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium\",\"volume\":\"20 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-04-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VTEST.1993.313313\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VTEST.1993.313313","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Analysis of redundant structures in combinational circuits
An efficient method for the analysis and detection of functionally equivalent nodes in combinational circuits is presented. In this work these nodes are called f-redundant nodes. The proposed method consists of two phases: First, a reduced set of pseudorandom input vectors is used to reduce the number of classes of nodes that are candidates for f-redundancy. In the second phase, ordered binary decision diagrams are used to check the equivalences between the logic functions of the remaining f-redundant node candidates. The efficiency of the proposed algorithm has been evaluated on the ISCAS'85 benchmark circuits.<>
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