利用泵送电容和线电感技术实现DC-DC升压变换器的超低电压纹波

Chen-Fan Tang, Ke-Horng Chen, Chinder Wey, Ying-Hsi Lin, Jian-Ru Lin, Tsung-Yen Tsai
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引用次数: 2

摘要

由于用于能量收集系统的传统DC-DC升压变换器在稳态和瞬态响应中存在较大的输出电压纹波,因此需要全面考虑包括键合线效应在内的因素。为此,本文提出了泵浦电容加线电感(PCWI)技术,将输出电压纹波抑制到超低值。通过一个额外的泵送电容(PC),可以确保小的稳态电压通过导线电感(WI)和连续WI电流。此外,即使在超低输出电压纹波的情况下,伪电感电流(PIC)技术也能重新生成电感电流信息,从而消除传统基于纹波控制技术的不稳定性问题。可同时减少暂态恢复时间和输出电压变化。将输入电压1.8 ~ 5.5 v转换为12.8V,采用0.18-μm 5V/24V CMOS工艺制备测试芯片。实验结果表明,输出电压纹波与输出电压的比值降至0.04%。测量的功率转换效率在100mA时约为92%,在0.1mA时为96%。
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Ultra-low voltage ripple in DC-DC boost converter by the pumping capacitor and wire inductance technique
Overall consideration including bonding wire effects is needed because conventional DC-DC boost converter used in energy harvesting systems suffers from large output voltage ripple in steady state and transient response. Thus, this paper proposed the pumping capacitor and wire inductance (PCWI) technique to suppress output voltage ripple to an ultra-low value. Small steady state voltage across the wire inductance (WI) and continuous WI current can be ensured by an additional pumping capacitor (PC). Moreover, even in case of an ultra-low output voltage ripple, the proposed pseudo-inductor current (PIC) technique regenerates the inductor current information to eliminate the instability problem in conventional ripple-based control techniques. Transient recovery time and output voltage variation can be reduced simultaneously. Test chip was fabricated in 0.18-μm 5V/24V CMOS process when input voltage of 1.8–5.5V is converted to 12.8V. Experimental results show the ratio of output voltage ripple and output voltage is reduced to 0.04%. Measured power conversion efficiency is around 92% at 100mA and 96% at 0.1mA.
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