{"title":"用于卫星通信的40纳米CMOS v波段功率放大器","authors":"Hengzhi Wan, Dixian Zhao","doi":"10.1109/ICTA56932.2022.9963077","DOIUrl":null,"url":null,"abstract":"This paper presents a V-band power amplifier (PA) with two stages. Each stage consists of a neutralized common-source amplifier pair, coupled with each other using a transformer. Implemented in 40-nm CMOS technology, the proposed two-stage PA achieves a measured small-signal gain of 16.8 dB at 47 GHz with a 3-dB bandwidth more than 6.5 GHz. The maximum 1-dB compressed output power (P1dB) is 12.2 dBm with a power-added efficiency at P1dB (PAE1dB) of 18% measured at 47 GHz; from 45 to 51 GHz, the measured P1dBis above 10 dBm under a 1.1-V supply voltage.","PeriodicalId":325602,"journal":{"name":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-10-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A V-band Power Amplifier for Satellite Communications in 40-nm CMOS\",\"authors\":\"Hengzhi Wan, Dixian Zhao\",\"doi\":\"10.1109/ICTA56932.2022.9963077\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a V-band power amplifier (PA) with two stages. Each stage consists of a neutralized common-source amplifier pair, coupled with each other using a transformer. Implemented in 40-nm CMOS technology, the proposed two-stage PA achieves a measured small-signal gain of 16.8 dB at 47 GHz with a 3-dB bandwidth more than 6.5 GHz. The maximum 1-dB compressed output power (P1dB) is 12.2 dBm with a power-added efficiency at P1dB (PAE1dB) of 18% measured at 47 GHz; from 45 to 51 GHz, the measured P1dBis above 10 dBm under a 1.1-V supply voltage.\",\"PeriodicalId\":325602,\"journal\":{\"name\":\"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)\",\"volume\":\"13 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-10-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICTA56932.2022.9963077\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICTA56932.2022.9963077","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A V-band Power Amplifier for Satellite Communications in 40-nm CMOS
This paper presents a V-band power amplifier (PA) with two stages. Each stage consists of a neutralized common-source amplifier pair, coupled with each other using a transformer. Implemented in 40-nm CMOS technology, the proposed two-stage PA achieves a measured small-signal gain of 16.8 dB at 47 GHz with a 3-dB bandwidth more than 6.5 GHz. The maximum 1-dB compressed output power (P1dB) is 12.2 dBm with a power-added efficiency at P1dB (PAE1dB) of 18% measured at 47 GHz; from 45 to 51 GHz, the measured P1dBis above 10 dBm under a 1.1-V supply voltage.
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