Estimation of maximum power and instantaneous current using a genetic algorithm

We present a genetic-algorithm-based approach for estimating the maximum power dissipation and instantaneous current through supply lines for CMOS circuits. Our approach can handle large combinational and sequential circuits with arbitrary but known delays. To obtain accurate results we extract the timing and current information from transistor-level and general-delay gate-level simulation. Our experimental results show that the patterns generated by our approach produce on the average a lower bound on the maximum power which is 41% tighter than the one obtained by weighted random patterns for estimating the maximum power. Also, our lower bound for the maximum instantaneous current is 21% tighter as compared to the weighted random patterns.