Architecting interconnect

Power is becoming the most significant limiter of processor performance, and increasing the ratio of logic versus cache transistors, as compared to the traditional roadmap, makes the situation worse. Also, the 5/spl times/ additional increase in I/O bandwidth requires significant extra power, putting a premium on signaling techniques that combine high per pin frequencies with low power per Gbit/s: However, limiting frequency improvements - to only 20% per year makes the situation better compared to historical growth rates and especially limits hot spot power densities. Nevertheless, the challenge to improve power efficiency, power delivery, and heat removal remains significant. Though mostly intended as a challenge to the EPEP community; my talk will also cover some of the advances made on addressing the main challenges and discusses some approaches to system and package design that may-help meet the challenges that remain.