Comparing The Performance Of A Low-power High Speed Flip-flop In Bulk And Soi Technologies

In this paper, the performance of double-edge triggered feedbacked flip-flop (DFFF) in SOI and bulk technologies has been compared. DFFF power consumption is reduced by avoiding unnecessary internal node transition. The subthreshold current in this flip-flop is very low compared to the other structures. Reducing the number of transistors in the stack and increasing the number of charge path lead to less delay and thus higher operational speed compared to the other flip-flops. By using SOI technology, the power consumption and speed have been improved further compared to bulk technology. The performance improvement is 37.10% to 45.54% for discussed flip-flops compared to bulk technology