A CAD approach for on-chip PDN with power and supply noise reduction for multi-voltage SOCS in pre-layout stage

This paper addresses a CAD implementation for power-efficient power-distribution network (PDN) design for multi-voltage system-on-chip (SoC) in pre-layout stage. High power efficiency and significant reduction in supply noise are achieved through optimization of different stages in PDN design for multi-voltage SoCs. The stages are a) selection of appropriate tree topology based on the multiple supply voltage (MSV), b) proper Vdd allocation for different functional modules, c) appropriate decoupling capacitance (Decap) allocation at pre-layout stage. In this paper, each of these three criteria has been taken care of to achieve higher power efficiency and satisfactory noise reduction in the PDN. The proposed PDN design is implemented for 1024 point FFT core. Experimental results demonstrate the efficacy of our proposed technique. The power is maximally reduced by 90.29% and average peak noise has been maximally suppressed by 98.53% at the pre-layout stage after allocation of multiple Vdd in the functional modules of FFT.