{"title":"超高速1k位RAM,存取时间7.5 ns","authors":"H. Mukai, K. Kawarada, K. Kondo, K. Toyoda","doi":"10.1109/ISSCC.1977.1155702","DOIUrl":null,"url":null,"abstract":"A 1024-BIT ECL RAM with typical address access time of 7.5 ns, faster than previously-reported RAMS’ will bc‘discussed. Write cycle time of 1 0 11s and write-enable pulsewidth of 3.5 ns are also possible. The memory consists of four blocks of each 256 words x 1 bit, which can be independently selected by four block select terminals, and therefore, may be used as either a 256 words x 4 bits or a 1024 words x 1 bit device. New circuit techniques, involving especially address decoders and sense amplifiers, as well as passive isolation technology and shallow diffusion processing were most helpful in achieving improved speed performance; Figure 1. The decoding circuit links a feedback loop from the collector circuit to the base of the multi-emitter transistor in each AND gate to equalize dc current distribution to these AND gates via a single current switch; minized too is the effective input logic swing of these gates. Thus, current mode operation, through driving of plural AND gates by condensed switching current, results in a very short delay time of 2.5 ns from address input t o word driver output, according to computer simulation. The common-basemode transistor switches connected between bit lines and sense circuits and cross-coupling between truth and complement in each sensing circuit reduce the undesirable effects of stray capacitances, resulting in a high sensing speed. The bit line clamping circuit is effective in quick recovery of bit line potential. Combination of the passive isolation of IOP (Isolated by Oxide and Polysilicon) with V-groove and the shallow, selfaligning emitter diffusion technique of DOPOS2 (Doped Poly Silicon) has made it possible to fabricate high-speed switching transistors with low parasitic capacitances ( CEB = 0.03 pF, CCB = 0.10 pF and C c s = 0.20 pF), high hFE (about 100) and high fT (2.0 GHz). Moreover, the memory cell size is now 2756 pm2; 52 p m x 53 pm. Minimum emitter size of IOPDOPOS transistors in this device is 3 p m x 8 pm. The memory","PeriodicalId":416313,"journal":{"name":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Ultra high speed 1K-bit RAM with 7.5 ns access time\",\"authors\":\"H. Mukai, K. Kawarada, K. Kondo, K. Toyoda\",\"doi\":\"10.1109/ISSCC.1977.1155702\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 1024-BIT ECL RAM with typical address access time of 7.5 ns, faster than previously-reported RAMS’ will bc‘discussed. Write cycle time of 1 0 11s and write-enable pulsewidth of 3.5 ns are also possible. The memory consists of four blocks of each 256 words x 1 bit, which can be independently selected by four block select terminals, and therefore, may be used as either a 256 words x 4 bits or a 1024 words x 1 bit device. New circuit techniques, involving especially address decoders and sense amplifiers, as well as passive isolation technology and shallow diffusion processing were most helpful in achieving improved speed performance; Figure 1. The decoding circuit links a feedback loop from the collector circuit to the base of the multi-emitter transistor in each AND gate to equalize dc current distribution to these AND gates via a single current switch; minized too is the effective input logic swing of these gates. Thus, current mode operation, through driving of plural AND gates by condensed switching current, results in a very short delay time of 2.5 ns from address input t o word driver output, according to computer simulation. The common-basemode transistor switches connected between bit lines and sense circuits and cross-coupling between truth and complement in each sensing circuit reduce the undesirable effects of stray capacitances, resulting in a high sensing speed. The bit line clamping circuit is effective in quick recovery of bit line potential. Combination of the passive isolation of IOP (Isolated by Oxide and Polysilicon) with V-groove and the shallow, selfaligning emitter diffusion technique of DOPOS2 (Doped Poly Silicon) has made it possible to fabricate high-speed switching transistors with low parasitic capacitances ( CEB = 0.03 pF, CCB = 0.10 pF and C c s = 0.20 pF), high hFE (about 100) and high fT (2.0 GHz). Moreover, the memory cell size is now 2756 pm2; 52 p m x 53 pm. Minimum emitter size of IOPDOPOS transistors in this device is 3 p m x 8 pm. The memory\",\"PeriodicalId\":416313,\"journal\":{\"name\":\"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"volume\":\"3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.1977.1155702\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1977 IEEE International Solid-State Circuits Conference. Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.1977.1155702","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Ultra high speed 1K-bit RAM with 7.5 ns access time
A 1024-BIT ECL RAM with typical address access time of 7.5 ns, faster than previously-reported RAMS’ will bc‘discussed. Write cycle time of 1 0 11s and write-enable pulsewidth of 3.5 ns are also possible. The memory consists of four blocks of each 256 words x 1 bit, which can be independently selected by four block select terminals, and therefore, may be used as either a 256 words x 4 bits or a 1024 words x 1 bit device. New circuit techniques, involving especially address decoders and sense amplifiers, as well as passive isolation technology and shallow diffusion processing were most helpful in achieving improved speed performance; Figure 1. The decoding circuit links a feedback loop from the collector circuit to the base of the multi-emitter transistor in each AND gate to equalize dc current distribution to these AND gates via a single current switch; minized too is the effective input logic swing of these gates. Thus, current mode operation, through driving of plural AND gates by condensed switching current, results in a very short delay time of 2.5 ns from address input t o word driver output, according to computer simulation. The common-basemode transistor switches connected between bit lines and sense circuits and cross-coupling between truth and complement in each sensing circuit reduce the undesirable effects of stray capacitances, resulting in a high sensing speed. The bit line clamping circuit is effective in quick recovery of bit line potential. Combination of the passive isolation of IOP (Isolated by Oxide and Polysilicon) with V-groove and the shallow, selfaligning emitter diffusion technique of DOPOS2 (Doped Poly Silicon) has made it possible to fabricate high-speed switching transistors with low parasitic capacitances ( CEB = 0.03 pF, CCB = 0.10 pF and C c s = 0.20 pF), high hFE (about 100) and high fT (2.0 GHz). Moreover, the memory cell size is now 2756 pm2; 52 p m x 53 pm. Minimum emitter size of IOPDOPOS transistors in this device is 3 p m x 8 pm. The memory