超高速1k位RAM,存取时间7.5 ns

H. Mukai, K. Kawarada, K. Kondo, K. Toyoda
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引用次数: 8

摘要

我们将讨论一个1024位ECL RAM,其典型的地址访问时间为7.5 ns,比以前报道的RAM快。写周期时间为1011秒,可写脉冲宽度为3.5 ns也是可能的。存储器由四个块组成,每个块256字× 1位,可由四个块选择终端独立选择,因此可以用作256字× 4位或1024字× 1位的设备。新的电路技术,特别是涉及地址解码器和感测放大器,以及被动隔离技术和浅扩散处理,对实现提高速度性能最有帮助;图1所示。解码电路将来自集电极电路的反馈回路连接到每个与门中的多发射极晶体管的基极,以通过单个电流开关均衡到这些与门的直流电流分布;这些门的有效输入逻辑摆幅也被最小化。因此,通过压缩开关电流驱动多个与门的电流模式操作,从地址输入到字驱动器输出的延迟时间非常短,仅为2.5 ns。位线与检测电路之间的共基模晶体管开关以及各检测电路中真值与补值之间的交叉耦合减少了杂散电容的不良影响,从而提高了检测速度。位线箝位电路能有效地快速恢复位线电位。结合v型沟槽IOP(由氧化物和多晶硅隔离)的被动隔离和DOPOS2(掺杂多晶硅)的浅自变发射极扩散技术,可以制造出具有低寄生电容(CEB = 0.03 pF, CCB = 0.10 pF和ccs = 0.20 pF),高hFE(约100)和高fT (2.0 GHz)的高速开关晶体管。此外,存储单元的尺寸现在是2756 pm2;下午52点乘下午53点。该器件中IOPDOPOS晶体管的最小发射极尺寸为3pm × 8pm。的内存
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Ultra high speed 1K-bit RAM with 7.5 ns access time
A 1024-BIT ECL RAM with typical address access time of 7.5 ns, faster than previously-reported RAMS’ will bc‘discussed. Write cycle time of 1 0 11s and write-enable pulsewidth of 3.5 ns are also possible. The memory consists of four blocks of each 256 words x 1 bit, which can be independently selected by four block select terminals, and therefore, may be used as either a 256 words x 4 bits or a 1024 words x 1 bit device. New circuit techniques, involving especially address decoders and sense amplifiers, as well as passive isolation technology and shallow diffusion processing were most helpful in achieving improved speed performance; Figure 1. The decoding circuit links a feedback loop from the collector circuit to the base of the multi-emitter transistor in each AND gate to equalize dc current distribution to these AND gates via a single current switch; minized too is the effective input logic swing of these gates. Thus, current mode operation, through driving of plural AND gates by condensed switching current, results in a very short delay time of 2.5 ns from address input t o word driver output, according to computer simulation. The common-basemode transistor switches connected between bit lines and sense circuits and cross-coupling between truth and complement in each sensing circuit reduce the undesirable effects of stray capacitances, resulting in a high sensing speed. The bit line clamping circuit is effective in quick recovery of bit line potential. Combination of the passive isolation of IOP (Isolated by Oxide and Polysilicon) with V-groove and the shallow, selfaligning emitter diffusion technique of DOPOS2 (Doped Poly Silicon) has made it possible to fabricate high-speed switching transistors with low parasitic capacitances ( CEB = 0.03 pF, CCB = 0.10 pF and C c s = 0.20 pF), high hFE (about 100) and high fT (2.0 GHz). Moreover, the memory cell size is now 2756 pm2; 52 p m x 53 pm. Minimum emitter size of IOPDOPOS transistors in this device is 3 p m x 8 pm. The memory
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