High mobility Ge pMOS fabricated using a novel heteroepitaxial ge on Si growth method

a) C. O. Chui was with the Dept. of EE at Stanford and is now with Intel Corporation, Santa Clara, CA 95054, USA b) T. Yonehara is with Leading-Edge Technology Development Headquarters, Canon Inc., 5-1, Morinosato-Wakamiya, Atsugi, Kanagawa 243-0193, Japan Abstract Using a novel multi-step in-situ growth and hydrogen annealing process heteroepitaxial-germanium layers have been grown directly on silicon, with defects confined near the Si/Ge interface, thus not threading to the surface as expected in this 4.2% lattice mismatched system. The results achieved are fully-relaxed smooth single crystal Ge layers on Si with defect density reduced to ~ 1 x 10 cm without a graded buffer layer or CMP step. To demonstrate the quality of the Ge layers, pMOSFETs have been fabricated using a sub-500 C process with low field mobility of ~250 cm/V-sec.