FinFET电路中栅极交叉缺陷的故障模拟与测试图生成

2015 IEEE 24th Asian Test Symposium (ATS) Pub Date : 2015-11-22 DOI:10.1109/ATS.2015.38

Kuan-Ying Chiang, Yu-Hao Ho, Yo-Wei Chen, Cheng-Sheng Pan, C. Li

{"title":"FinFET电路中栅极交叉缺陷的故障模拟与测试图生成","authors":"Kuan-Ying Chiang, Yu-Hao Ho, Yo-Wei Chen, Cheng-Sheng Pan, C. Li","doi":"10.1109/ATS.2015.38","DOIUrl":null,"url":null,"abstract":"A FAST fault model is proposed for small delay faults induced by cross-gate defects in FinFET. FAST ATPG, fault simulation, and test selection are presented to generate and select test patterns to detect FAST faults. Experiments on large benchmark circuits show that our pattern sets have approximately 29% and 4% better FAST coverage and FAST SDQL respectively than those of commercial tool timing-unaware 1-detect pattern sets.","PeriodicalId":256879,"journal":{"name":"2015 IEEE 24th Asian Test Symposium (ATS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits\",\"authors\":\"Kuan-Ying Chiang, Yu-Hao Ho, Yo-Wei Chen, Cheng-Sheng Pan, C. Li\",\"doi\":\"10.1109/ATS.2015.38\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A FAST fault model is proposed for small delay faults induced by cross-gate defects in FinFET. FAST ATPG, fault simulation, and test selection are presented to generate and select test patterns to detect FAST faults. Experiments on large benchmark circuits show that our pattern sets have approximately 29% and 4% better FAST coverage and FAST SDQL respectively than those of commercial tool timing-unaware 1-detect pattern sets.\",\"PeriodicalId\":256879,\"journal\":{\"name\":\"2015 IEEE 24th Asian Test Symposium (ATS)\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-11-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE 24th Asian Test Symposium (ATS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATS.2015.38\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE 24th Asian Test Symposium (ATS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.2015.38","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 8

摘要

针对FinFET中交叉栅缺陷引起的小延迟故障，提出了一种FAST故障模型。提出了FAST ATPG、故障模拟和测试选择来生成和选择测试模式以检测FAST故障。在大型基准电路上的实验表明，我们的模式集的FAST覆盖率和FAST SDQL分别比商业工具时间不感知的1检测模式集高约29%和4%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

Fault Simulation and Test Pattern Generation for Cross-gate Defects in FinFET Circuits

A FAST fault model is proposed for small delay faults induced by cross-gate defects in FinFET. FAST ATPG, fault simulation, and test selection are presented to generate and select test patterns to detect FAST faults. Experiments on large benchmark circuits show that our pattern sets have approximately 29% and 4% better FAST coverage and FAST SDQL respectively than those of commercial tool timing-unaware 1-detect pattern sets.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2015 IEEE 24th Asian Test Symposium (ATS)

自引率

0.00%

发文量