A method for synchronizing IEEE 1149.1 test access port for chip level testability access

This paper presents a novel method for using the industry standard IEEE Std. 1149.1 test port for accessing chip-wide testability features. The scheme reconfigures the test port to switch its normal asynchronous-to-chip-logic operating mode to a special synchronous-to-chip-logic operating mode that can be exploited in chip-alone test environments. The method allows the internal testability features to be designed normally and operated at full speed in chip's native clock domain.