156mbit /s的3R单片CMOS集成电路

Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434) Pub Date : 2000-08-28 DOI:10.1109/APASIC.2000.896933

D. Yamazaki, S. Ide, T. Chiba, A. Hayakawa, H. Rokugawa, M. Kawai

{"title":"156mbit /s的3R单片CMOS集成电路","authors":"D. Yamazaki, S. Ide, T. Chiba, A. Hayakawa, H. Rokugawa, M. Kawai","doi":"10.1109/APASIC.2000.896933","DOIUrl":null,"url":null,"abstract":"A 3R one chip IC at 156 Mbit/s using PLL retiming technology has been fabricated with a 0.35 /spl mu/m CMOS. We developed a new voltage controlled oscillator (VCO) that has less deviation of free run frequency so that any adjustment is not required. We have also developed a wide dynamic range preamplifier. The use of this preamplifier and VCO realizes a 38 dB dynamic range without any requirement for adjustment of a PLL.","PeriodicalId":313978,"journal":{"name":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-08-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"3R one chip CMOS IC at 156 Mbit/s\",\"authors\":\"D. Yamazaki, S. Ide, T. Chiba, A. Hayakawa, H. Rokugawa, M. Kawai\",\"doi\":\"10.1109/APASIC.2000.896933\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 3R one chip IC at 156 Mbit/s using PLL retiming technology has been fabricated with a 0.35 /spl mu/m CMOS. We developed a new voltage controlled oscillator (VCO) that has less deviation of free run frequency so that any adjustment is not required. We have also developed a wide dynamic range preamplifier. The use of this preamplifier and VCO realizes a 38 dB dynamic range without any requirement for adjustment of a PLL.\",\"PeriodicalId\":313978,\"journal\":{\"name\":\"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-08-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/APASIC.2000.896933\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/APASIC.2000.896933","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

利用锁相环重定时技术，采用0.35 /spl μ m CMOS，制作了156mbit /s的3R单片集成电路。我们开发了一种新的电压控制振荡器(VCO)，它具有较小的自由运行频率偏差，因此不需要任何调整。我们还开发了一种宽动态范围前置放大器。使用该前置放大器和压控振荡器实现38db动态范围，无需调整锁相环。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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3R one chip CMOS IC at 156 Mbit/s

A 3R one chip IC at 156 Mbit/s using PLL retiming technology has been fabricated with a 0.35 /spl mu/m CMOS. We developed a new voltage controlled oscillator (VCO) that has less deviation of free run frequency so that any adjustment is not required. We have also developed a wide dynamic range preamplifier. The use of this preamplifier and VCO realizes a 38 dB dynamic range without any requirement for adjustment of a PLL.

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Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)

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