Advanced Phase Jitter Analysis with Power Noise Induced Jitter Flow in PCIe Gen 3

In this work, we present a method to derive the phase jitter (PJ) of PCI Express (PCIe) Gen3 by analyzing both random jitter (RJ) and deterministic jitter (DJ) induced by power noise in a clock network. In the previous jitter analysis methods, the impact of power noise has not been considered when analyzing the jitter of PCIe Gen3 reference clock networks. We apply the proposed method to analyze and validate the main noise sources of PCIe Gen3 PJ violations observed in a system-on-chip (SoC) design implemented at Samsung's 4-nanometer process node. Through various experiments, we found that the main cause of the violation is jitter due to power noise below 50 MHz. By modifying the power management integrated circuit (PMIC) to reduce the low-frequency noise at the PMIC output, we observed a 50% reduction in jitter in the clock network.