合并电流模式逻辑

1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers Pub Date : 1900-01-01 DOI:10.1109/ISSCC.1984.1156657

P. Zdebel, W. Engl

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引用次数: 4

摘要

本文将描述使用上下晶体管形成不饱和和合并的电流模式逻辑，在功耗小于50μW/栅极时产生0.1pJ的功率延迟积，在200μW/栅极时产生1.6ns的最小延迟。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Merged current mode logic

The use of down and up transistors to form nonsaturating and merged current mode logic resulting in a power-delay product of 0.1pJ for power dissipation less than 50μW/gate and a minimum delay of 1.6ns at 200μW/gate will be described.

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1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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