Huajun Chen, Zhenqi Chen, Rongde Ou, Run Chen, Zhaohui Wu, Bin Li
{"title":"基于28nm CMOS的4- 9ghz IEEE 802.15.4z兼容超宽带数字发射机,可重构脉冲整形","authors":"Huajun Chen, Zhenqi Chen, Rongde Ou, Run Chen, Zhaohui Wu, Bin Li","doi":"10.1109/RFIC54546.2022.9862953","DOIUrl":null,"url":null,"abstract":"This paper presents an IEEE 802.15.4z standard-compliant UWB digital transmitter that features reconfigurable pulse-shaping. The proposed UWB pulse-shaping technique exploits programmable delay lines to achieve high spectrum efficiency and significant sidelobe suppression. An on-chip broadband matching network with a second-harmonic trap is implemented to protect the digital power amplifier (DPA) realized by thin-gate transistors. Implemented in a 28nm CMOS process with a supply voltage of 0.9V, the prototype chip can operate from 4 to 9 GHz at various pulse repetition rates (PRF) from 1 to 249.6 MHz with programmable signal bandwidths (500 ∼ 1331 MHz). The measured transmitted waveform meets with IEEE 802.15.4z standard, and its spectrum efficiency is up to 59%. The output power is highly programmable with a peak value of 14.5 dBm.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A 4-to-9GHz IEEE 802.15.4z-Compliant UWB Digital Transmitter with Reconfigurable Pulse-Shaping in 28nm CMOS\",\"authors\":\"Huajun Chen, Zhenqi Chen, Rongde Ou, Run Chen, Zhaohui Wu, Bin Li\",\"doi\":\"10.1109/RFIC54546.2022.9862953\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents an IEEE 802.15.4z standard-compliant UWB digital transmitter that features reconfigurable pulse-shaping. The proposed UWB pulse-shaping technique exploits programmable delay lines to achieve high spectrum efficiency and significant sidelobe suppression. An on-chip broadband matching network with a second-harmonic trap is implemented to protect the digital power amplifier (DPA) realized by thin-gate transistors. Implemented in a 28nm CMOS process with a supply voltage of 0.9V, the prototype chip can operate from 4 to 9 GHz at various pulse repetition rates (PRF) from 1 to 249.6 MHz with programmable signal bandwidths (500 ∼ 1331 MHz). The measured transmitted waveform meets with IEEE 802.15.4z standard, and its spectrum efficiency is up to 59%. The output power is highly programmable with a peak value of 14.5 dBm.\",\"PeriodicalId\":415294,\"journal\":{\"name\":\"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-06-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RFIC54546.2022.9862953\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIC54546.2022.9862953","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 4-to-9GHz IEEE 802.15.4z-Compliant UWB Digital Transmitter with Reconfigurable Pulse-Shaping in 28nm CMOS
This paper presents an IEEE 802.15.4z standard-compliant UWB digital transmitter that features reconfigurable pulse-shaping. The proposed UWB pulse-shaping technique exploits programmable delay lines to achieve high spectrum efficiency and significant sidelobe suppression. An on-chip broadband matching network with a second-harmonic trap is implemented to protect the digital power amplifier (DPA) realized by thin-gate transistors. Implemented in a 28nm CMOS process with a supply voltage of 0.9V, the prototype chip can operate from 4 to 9 GHz at various pulse repetition rates (PRF) from 1 to 249.6 MHz with programmable signal bandwidths (500 ∼ 1331 MHz). The measured transmitted waveform meets with IEEE 802.15.4z standard, and its spectrum efficiency is up to 59%. The output power is highly programmable with a peak value of 14.5 dBm.