{"title":"具有SIMD架构和快速3D功能的双问题浮点协处理器","authors":"R. Rogenmoser, L. O'Donnell, S. Nishimoto","doi":"10.1109/ISSCC.2002.993108","DOIUrl":null,"url":null,"abstract":"A floating-point coprocessor, part of a MIPS64 dual-processor SOC, consists of a 32/spl times/64b register file and two pipes each with a multiplier, an adder, and a fast 3D approximation unit. It operates up to 1 GHz at 1.3 W, measures 4.74 mm/sup 2/ in 0.13 /spl mu/m CMOS, and has peak performance of 8 GFlops per CPU and 16 GFlops on the dual-processor SOC.","PeriodicalId":423674,"journal":{"name":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"A dual-issue floating-point coprocessor with SIMD architecture and fast 3D functions\",\"authors\":\"R. Rogenmoser, L. O'Donnell, S. Nishimoto\",\"doi\":\"10.1109/ISSCC.2002.993108\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A floating-point coprocessor, part of a MIPS64 dual-processor SOC, consists of a 32/spl times/64b register file and two pipes each with a multiplier, an adder, and a fast 3D approximation unit. It operates up to 1 GHz at 1.3 W, measures 4.74 mm/sup 2/ in 0.13 /spl mu/m CMOS, and has peak performance of 8 GFlops per CPU and 16 GFlops on the dual-processor SOC.\",\"PeriodicalId\":423674,\"journal\":{\"name\":\"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSCC.2002.993108\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSCC.2002.993108","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A dual-issue floating-point coprocessor with SIMD architecture and fast 3D functions
A floating-point coprocessor, part of a MIPS64 dual-processor SOC, consists of a 32/spl times/64b register file and two pipes each with a multiplier, an adder, and a fast 3D approximation unit. It operates up to 1 GHz at 1.3 W, measures 4.74 mm/sup 2/ in 0.13 /spl mu/m CMOS, and has peak performance of 8 GFlops per CPU and 16 GFlops on the dual-processor SOC.
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