利用单层短流NEST结构快速提取致命缺陷密度和尺寸分布

C. Hess, D. Stashower, B. Stine, G. Verna, L. Weiland, K. Miyamoto, K. Inoue
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引用次数: 9

摘要

缺陷检测是过程控制和提高晶片良率所必需的。测试结构的电气测量通常用于检测故障。为了提高基于电的缺陷密度和缺陷尺寸分布测定的准确性,我们提出了一种新的NEST结构。在那里,许多嵌套的蛇形线将被放置在一个单层中。该掩码将用作短流,以保证快速过程数据提取的短周转时间。数据分析程序将提供对产品晶片良率有影响的致命缺陷的密度和尺寸分布。
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Fast extraction of killer defect density and size distribution using a single layer short flow NEST structure
Defect inspection is required for process control and to enhance chip yield. Electrical measurements of test structures are commonly used to detect faults. To improve accuracy of electrically based determination of defect densities and defect size distributions, we present a novel NEST structure. There, many nested serpentine lines will be placed within a single layer only. This mask will be used as a short flow to guarantee a short turn around time for fast process data extraction. Data analysis procedures will provide densities and size distributions of killer defects that will have an impact on product chip yield.
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