{"title":"从时间正则表达式生成在线测试向量","authors":"Y. Oddos, K. Morin-Allory, D. Bomone","doi":"10.1109/IWSOC.2006.348223","DOIUrl":null,"url":null,"abstract":"The authors propose an efficient solution to automatically generate test vectors that satisfy an assumed property written in PSL. From a SERE formula, the authors build a synthesizable generator that produces random temporal test vectors compliant with the formula. Generators are space and speed efficient when synthesized on FPGA, and their connection to the device under test is a portable solution across verification platforms for simulation and emulation","PeriodicalId":134742,"journal":{"name":"2006 6th International Workshop on System on Chip for Real Time Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"On-Line Test Vector Generation from Temporal Regular Expressions\",\"authors\":\"Y. Oddos, K. Morin-Allory, D. Bomone\",\"doi\":\"10.1109/IWSOC.2006.348223\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The authors propose an efficient solution to automatically generate test vectors that satisfy an assumed property written in PSL. From a SERE formula, the authors build a synthesizable generator that produces random temporal test vectors compliant with the formula. Generators are space and speed efficient when synthesized on FPGA, and their connection to the device under test is a portable solution across verification platforms for simulation and emulation\",\"PeriodicalId\":134742,\"journal\":{\"name\":\"2006 6th International Workshop on System on Chip for Real Time Applications\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 6th International Workshop on System on Chip for Real Time Applications\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IWSOC.2006.348223\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 6th International Workshop on System on Chip for Real Time Applications","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWSOC.2006.348223","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
On-Line Test Vector Generation from Temporal Regular Expressions
The authors propose an efficient solution to automatically generate test vectors that satisfy an assumed property written in PSL. From a SERE formula, the authors build a synthesizable generator that produces random temporal test vectors compliant with the formula. Generators are space and speed efficient when synthesized on FPGA, and their connection to the device under test is a portable solution across verification platforms for simulation and emulation
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