一个6位，7mW, 250fJ, 700MS/s的变换ADC

2009 IEEE Asian Solid-State Circuits Conference Pub Date : 2009-12-22 DOI:10.1109/ASSCC.2009.5357198

Y. Asada, K. Yoshihara, Tatsuya Urano, M. Miyahara, A. Matsuzawa

{"title":"一个6位，7mW, 250fJ, 700MS/s的变换ADC","authors":"Y. Asada, K. Yoshihara, Tatsuya Urano, M. Miyahara, A. Matsuzawa","doi":"10.1109/ASSCC.2009.5357198","DOIUrl":null,"url":null,"abstract":"A 6 bit, 7 mW, 700 MS /s subranging ADC fabricated in 90 nm CMOS technology with SNDR of 34 dB for Nyquist input frequency is presented. The subranging architecture using CDACs, gate-weighted interpolation scheme, and digitally offset calibrating double-tail latched comparators has demonstrated an ultra low FoM of 250 fJ/conv. steps. and attractiveness for embedded IP for low power SoCs.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"19","resultStr":"{\"title\":\"A 6bit, 7mW, 250fJ, 700MS/s subranging ADC\",\"authors\":\"Y. Asada, K. Yoshihara, Tatsuya Urano, M. Miyahara, A. Matsuzawa\",\"doi\":\"10.1109/ASSCC.2009.5357198\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 6 bit, 7 mW, 700 MS /s subranging ADC fabricated in 90 nm CMOS technology with SNDR of 34 dB for Nyquist input frequency is presented. The subranging architecture using CDACs, gate-weighted interpolation scheme, and digitally offset calibrating double-tail latched comparators has demonstrated an ultra low FoM of 250 fJ/conv. steps. and attractiveness for embedded IP for low power SoCs.\",\"PeriodicalId\":263023,\"journal\":{\"name\":\"2009 IEEE Asian Solid-State Circuits Conference\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-12-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"19\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 IEEE Asian Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2009.5357198\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2009.5357198","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 19

摘要

提出了一种采用90nm CMOS技术制作的6位、7mw、700ms /s的分位ADC，在Nyquist输入频率下SNDR为34 dB。采用CDACs、门加权插值方案和数字偏置校准双尾锁存比较器的分位结构证明了250 fJ/conv的超低FoM。步骤。以及低功耗soc的嵌入式IP的吸引力。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 6bit, 7mW, 250fJ, 700MS/s subranging ADC

A 6 bit, 7 mW, 700 MS /s subranging ADC fabricated in 90 nm CMOS technology with SNDR of 34 dB for Nyquist input frequency is presented. The subranging architecture using CDACs, gate-weighted interpolation scheme, and digitally offset calibrating double-tail latched comparators has demonstrated an ultra low FoM of 250 fJ/conv. steps. and attractiveness for embedded IP for low power SoCs.

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2009 IEEE Asian Solid-State Circuits Conference

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