硅功率器件堆叠芯片寄生电阻的测量

2023 35th International Conference on Microelectronic Test Structure (ICMTS) Pub Date : 2023-03-27 DOI:10.1109/ICMTS55420.2023.10094137

T. Ohguro, Hideharu Kojima, T. Hara, T. Nishiwaki, Kenya Kobayashi

{"title":"硅功率器件堆叠芯片寄生电阻的测量","authors":"T. Ohguro, Hideharu Kojima, T. Hara, T. Nishiwaki, Kenya Kobayashi","doi":"10.1109/ICMTS55420.2023.10094137","DOIUrl":null,"url":null,"abstract":"Stacked chip of! Si power device is useful for both lower on-resistance and small packaged size for reduction of system size and high power efficiency. In this paper, some structures and procedure to measure parasitic resistance of the stacked chip are described.","PeriodicalId":275144,"journal":{"name":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Measuring of parasitic resistance of stacked chip of Si power device\",\"authors\":\"T. Ohguro, Hideharu Kojima, T. Hara, T. Nishiwaki, Kenya Kobayashi\",\"doi\":\"10.1109/ICMTS55420.2023.10094137\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Stacked chip of! Si power device is useful for both lower on-resistance and small packaged size for reduction of system size and high power efficiency. In this paper, some structures and procedure to measure parasitic resistance of the stacked chip are described.\",\"PeriodicalId\":275144,\"journal\":{\"name\":\"2023 35th International Conference on Microelectronic Test Structure (ICMTS)\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-03-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2023 35th International Conference on Microelectronic Test Structure (ICMTS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICMTS55420.2023.10094137\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 35th International Conference on Microelectronic Test Structure (ICMTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMTS55420.2023.10094137","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

叠芯片的!硅功率器件具有导通电阻低、封装尺寸小等优点，可减小系统尺寸，提高功率效率。本文介绍了叠片寄生电阻的测量方法和结构。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

Measuring of parasitic resistance of stacked chip of Si power device

Stacked chip of! Si power device is useful for both lower on-resistance and small packaged size for reduction of system size and high power efficiency. In this paper, some structures and procedure to measure parasitic resistance of the stacked chip are described.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2023 35th International Conference on Microelectronic Test Structure (ICMTS)

自引率

0.00%

发文量