High-Level Design of a 14-bit Continuous-Time Sigma-Delta Modulator with FIR DAC for Low-Voltage Audio Devices

Currently, mobile and wearable devices have digital audio signal processing capabilities. Since the nature of audio signals is analog, there is a need to use analog-to-digital converters (ADCs) with high-resolution for a high signal-to-noise ratio audio acquisition. This paper presents the high-level design of a continuous-time third-order sigma-delta modulator with a FIR DAC for audio devices, using a supply voltage of 0.5 V. The design is carried out using the Delta-sigma toolbox and a discrete-time to continuous-time (DT-CT) transformation. It was estimated that the first-integrator amplifier needs a gain of 50 dB, a GBW of 5 MHz and a slew-rate of at least $3\ \mathrm{V}/\mu \mathrm{s}$. By implementing this amplifier in VerilogA and performing a transient simulation with noise, the modulator obtained an SNR of 86.63 dB, an SNDR of 86.46 dB and an ENOB of 14.07 bits. Finally, the extraction of the initial parameters for the amplifier design proved to be satisfactory, since the modulator performance results were within the specified in the design.