{"title":"基于δ - σ调制器的d类放大器","authors":"Chien-Hung Kuo, Shengyue Lin","doi":"10.1109/GCCE.2016.7800440","DOIUrl":null,"url":null,"abstract":"A new architecture of class-D amplifier with a multibit delta-sigma modulator control is presented in this paper. In the presented amplifier, the 3-bit 8-level digital outputs of the second-order delta-sigma modulator are utilized to generate switching signals with different pulse widths for the class-D power amplifier. A closed-loop class-D amplifier is adopted by feeding the analog output signal from the power stage to the input to improve the linearity. The presented class-D amplifier is simulated with TSMC 0.18-μm CMOS process. The SNDR of the proposed amplifier is 78 dB within a 25 kHz signal bandwidth under a sample rate of 2.56 MHz. The THD is 0.01% at a power consumption of 140 mW.","PeriodicalId":416104,"journal":{"name":"2016 IEEE 5th Global Conference on Consumer Electronics","volume":"38 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-12-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A delta-sigma modulator-based class-D amplifier\",\"authors\":\"Chien-Hung Kuo, Shengyue Lin\",\"doi\":\"10.1109/GCCE.2016.7800440\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new architecture of class-D amplifier with a multibit delta-sigma modulator control is presented in this paper. In the presented amplifier, the 3-bit 8-level digital outputs of the second-order delta-sigma modulator are utilized to generate switching signals with different pulse widths for the class-D power amplifier. A closed-loop class-D amplifier is adopted by feeding the analog output signal from the power stage to the input to improve the linearity. The presented class-D amplifier is simulated with TSMC 0.18-μm CMOS process. The SNDR of the proposed amplifier is 78 dB within a 25 kHz signal bandwidth under a sample rate of 2.56 MHz. The THD is 0.01% at a power consumption of 140 mW.\",\"PeriodicalId\":416104,\"journal\":{\"name\":\"2016 IEEE 5th Global Conference on Consumer Electronics\",\"volume\":\"38 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-12-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE 5th Global Conference on Consumer Electronics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/GCCE.2016.7800440\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE 5th Global Conference on Consumer Electronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GCCE.2016.7800440","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A new architecture of class-D amplifier with a multibit delta-sigma modulator control is presented in this paper. In the presented amplifier, the 3-bit 8-level digital outputs of the second-order delta-sigma modulator are utilized to generate switching signals with different pulse widths for the class-D power amplifier. A closed-loop class-D amplifier is adopted by feeding the analog output signal from the power stage to the input to improve the linearity. The presented class-D amplifier is simulated with TSMC 0.18-μm CMOS process. The SNDR of the proposed amplifier is 78 dB within a 25 kHz signal bandwidth under a sample rate of 2.56 MHz. The THD is 0.01% at a power consumption of 140 mW.
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