Reducing IR drop in 3D integration to less than 1/4 using Buck Converter on Top die (BCT) scheme

This paper proposes a method to reduce the supply voltage IR drop of 3D stacked-die systems by implementing an on-chip Buck Converter on Top die (BCT) scheme. The IR drop is caused by the parasitic resistance of Through Silicon Vias (TSV's) used in the 3D integration. The IR drop reduction and the overhead associated with the BCT scheme are modeled and analyzed. A 3D stacked-die system is manufactured using 90nm CMOS technology with TSV's and a silicon interposer. A chip inductor and chip capacitors for the buck converter are mounted directly on the top die. The reduction of the IR drop to less than 1/4 is verified through experiments.