两步量化多比特信号调制器的抽取滤波器设计

Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006. Pub Date : 2006-06-22 DOI:10.1109/MIXDES.2006.1706663

A. Kuncheva, L. Fujcik, T. Mougel, B. Donchev, M. Hristov

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引用次数: 2

摘要

本文介绍了用VHDL语言设计用于多位σ - δ (SigmaDelta)调制器的数字抽取滤波器的步骤。抽取滤波器的参数根据两步量化结构的多比特SigmaDelta调制器的规格推导。使用Matlab工具，可以找到滤波器的顺序，所需的量化水平的系数和它们的值。最后，通过对设计的分析，找到了一种有效的硬件实现方法。该结构用VHDL设计了两个版本。该设计在Xilinx FPGA -Spartan 3 XC3S200-5FT256上进行了编程和测试

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Design Of Decimation Filter For Multibit Sigmadelta Modulator With Two-step Quantization

This paper describes steps involved in a VHDL design of digital decimation filter for multibit sigma-delta (SigmaDelta) modulator. Parameters of decimation filter are derived from the specification of the multibit SigmaDelta modulator with two-step quantization architecture. Using Matlab tool it is possible to find the filter order, the required quantization level for the coefficients and their values. Finally, by analyzing the design, we can find an efficient way to implement the filter in hardware. This structure is designed in two versions using VHDL. The design is programmed and tested on a Xilinx FPGA -Spartan 3 XC3S200-5FT256

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Proceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006.

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