Hongxin Tang, H. Qian, Bingzheng Yang, Tianyi Wang, Xun Luo
{"title":"一种支持64-/256-/1024-QAM的4.4°AM-PM失真的片上自校准极化Doherty SCPA","authors":"Hongxin Tang, H. Qian, Bingzheng Yang, Tianyi Wang, Xun Luo","doi":"10.1109/RFIC54546.2022.9863144","DOIUrl":null,"url":null,"abstract":"In this paper, an efficient switched-capacitor power amplifier (SCPA) with high linearity using on-chip self-calibration technique is proposed. The inherent AM-PM distortion in digital power amplifier (DPA) is decreased by the proposed self-calibration technique without any pre-distortion. Meanwhile, to improve the modulation bandwidth, a storage capacitor array (SCA) is introduced to decrease the settle-time of the calibration loop for transition among various baseband signals. The proposed polar Doherty SCPA is implemented in conventional 40-nm CMOS technology. It operates in 1.4-2.8 GHz with peak output power of 28.9 dBm, peak drain efficiency (DE) of 43.9%, peak system efficiency (SE) of 37.2%, and AM-PM distortion of 4.4°at 1.8 GHz. It supports 100 MHz 64-QAM signal (i.e., 22.6 dBm average output power, 4.87% EVM, and 33.9% average DE) and 10 MHz 1024-QAM signal (i.e., 21.3 dBm average output power, 1.77% EVM, and 32.1 % average DE) without any pre-distortion.","PeriodicalId":415294,"journal":{"name":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-06-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A Polar Doherty SCPA with 4.4°AM-PM Distortion Using On-Chip Self-Calibration Supporting 64-/256-/1024-QAM\",\"authors\":\"Hongxin Tang, H. Qian, Bingzheng Yang, Tianyi Wang, Xun Luo\",\"doi\":\"10.1109/RFIC54546.2022.9863144\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, an efficient switched-capacitor power amplifier (SCPA) with high linearity using on-chip self-calibration technique is proposed. The inherent AM-PM distortion in digital power amplifier (DPA) is decreased by the proposed self-calibration technique without any pre-distortion. Meanwhile, to improve the modulation bandwidth, a storage capacitor array (SCA) is introduced to decrease the settle-time of the calibration loop for transition among various baseband signals. The proposed polar Doherty SCPA is implemented in conventional 40-nm CMOS technology. It operates in 1.4-2.8 GHz with peak output power of 28.9 dBm, peak drain efficiency (DE) of 43.9%, peak system efficiency (SE) of 37.2%, and AM-PM distortion of 4.4°at 1.8 GHz. It supports 100 MHz 64-QAM signal (i.e., 22.6 dBm average output power, 4.87% EVM, and 33.9% average DE) and 10 MHz 1024-QAM signal (i.e., 21.3 dBm average output power, 1.77% EVM, and 32.1 % average DE) without any pre-distortion.\",\"PeriodicalId\":415294,\"journal\":{\"name\":\"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2022-06-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RFIC54546.2022.9863144\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIC54546.2022.9863144","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A Polar Doherty SCPA with 4.4°AM-PM Distortion Using On-Chip Self-Calibration Supporting 64-/256-/1024-QAM
In this paper, an efficient switched-capacitor power amplifier (SCPA) with high linearity using on-chip self-calibration technique is proposed. The inherent AM-PM distortion in digital power amplifier (DPA) is decreased by the proposed self-calibration technique without any pre-distortion. Meanwhile, to improve the modulation bandwidth, a storage capacitor array (SCA) is introduced to decrease the settle-time of the calibration loop for transition among various baseband signals. The proposed polar Doherty SCPA is implemented in conventional 40-nm CMOS technology. It operates in 1.4-2.8 GHz with peak output power of 28.9 dBm, peak drain efficiency (DE) of 43.9%, peak system efficiency (SE) of 37.2%, and AM-PM distortion of 4.4°at 1.8 GHz. It supports 100 MHz 64-QAM signal (i.e., 22.6 dBm average output power, 4.87% EVM, and 33.9% average DE) and 10 MHz 1024-QAM signal (i.e., 21.3 dBm average output power, 1.77% EVM, and 32.1 % average DE) without any pre-distortion.