柔性混合集成芯片箔封装的动态弯曲可靠性分析

N. Palavesam, E. Yacoub-George, W. Hell, C. Landesberger, C. Kutter, K. Bock
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引用次数: 5

摘要

近年来,随着物联网(IoT)和可穿戴设备的出现,柔性混合电子(FHEs)引起了人们的广泛关注。芯片箔封装(也称为柔性中间体)通过将超薄硅集成电路集成到或嵌入到由金属互连(布线线,通孔通过互连等)组成的聚合物箔上制造,用于为系统供电和数据信号/ IO命令传输,是FHE集成的理想候选者。与标准表面贴装器件(SMD)组件相比,芯片箔封装的主要优点是其弯曲能力和一致性。然而,芯片箔封装在反复弯曲下的行为必须通过广泛的调查来详细分析,以使技术从研究实验室转移到工业制造平台。因此,我们进行了两种不同类型的弯曲测试,以检查布线线和芯片箔封装的过孔互连的重复或动态弯曲可靠性。实验结果表明,为了制造具有高性能和良好动态弯曲可靠性的FHEs,需要优化布线和通孔互连的尺寸。这些结果补充了关于芯片箔封装的电气和机械可靠性的最新信息,并且是在集成过程中建立处理芯片箔封装指南以及生产更可靠的fhe所需的基本信息。
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Dynamic Bending Reliability Analysis of Flexible Hybrid Integrated Chip-Foil Packages
With the emergence of the Internet-of-Things (IoT) and wearable devices in the recent years, Flexible Hybrid Electronics (FHEs) has attracted significant attention. Chip-foil packages (also known as flexible interposers) fabricated by integrating ultra-thin silicon ICs onto or embedded into polymer foils comprising of metal interconnects (wiring lines, through hole via interconnects etc.) for powering up the system and transmission of data signals / IO commands are ideal candidates for FHE integration. The principal advantages of chip-foil packages over standard Surface Mount Device (SMD) components are their bend ability and conformability. However, the behavior of chip-foil packages under repeated bending must be analyzed in detail through extensive investigations to enable the transfer of the technology from research labs to industrial manufacturing platforms. Hence, we conducted two different types of bending tests to examine the repeated or dynamic bending reliability of the wiring lines and the via interconnects of the chip-foil packages. The experimental results highlight the need for design optimized dimensioning of the wiring lines and the via interconnects for manufacturing FHEs with high performance and good dynamic bending reliability. Such results complement the state-of-the-art information available regarding the electrical as well as mechanical reliability of chip-foil packages and are required as essential information for establishing guidelines for handling chip-foil packages during integration as well as for producing FHEs that are more reliable.
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